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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com cs5376a low power multi-channel decimation filter features 1 to 4 channel digital decimation filter multiple on-chip fir and iir coefficient sets programmable coefficients for custom filters synchronous operation selectable output word rate 4000, 2000, 1000, 500, 333, 250 sps 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 sps digital gain and offset corrections test dac bit stream generator sine wave or impulse output mode time break controller, general purpose i/o secondary spi port, boundary scan jtag microcontroller or eeprom configuration small footprint 64-pin tqfp package low power consumption 9 mw per channel at 500 sps flexible power supplies i/o interface: 3.3 v or 5.0 v digital logic core: 3.0 v, 3.3 v or 5.0 v description the cs5376a is a multi-function digital filter utilizing a low-power signal processing architecture to achieve effi- cient filtering for up to four ? modulators. by combining the cs5376a with cs3301/02 differential amplifiers, cs5371/72 ? modulators, and the cs4373 ? test dac a synchronous high resolution multi-channel mea- surement system can be designed quickly and easily. digital filter coefficients for the cs5376a fir and iir fil- ters are included on-chip for a simple setup, or they can be programmed for custom applications. selectable dig- ital filter decimation ratios produce output word rates from 4000 sps to 1 sps, resulting in measurement bandwidths ranging from 1600 hz down to 400 mhz when using the on-chip coefficient sets. the cs5376a includes integrated peripherals to simplify system design: offset and gain corrections, a test dac bit stream generator, a time break controller, 12 general purpose i/o pins, a secondary spi port, and a boundary scan jtag port. ordering information CS5376A-IQ -40 to +85 o c 64-pin tqfp i sck1 s erial da ta o utput p ort decimation and filtering e ngine modulator data interface test bit stream controller clock and synchronization tbsclk tbsdata spi 1 serial peripheral interface 1 jtag interface tim e break controller spi 2 serial peripheral interface 2 gpio general p urpose i/o sdclk sddat sdtki boot vd (x2) vdd1 vdd2 (x2) sync clk mclk msync timeb miso mosi ssi sint sdrdy sck2 so si1 si2 si3 si4 gpio11:eecs gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4:cs4 gpio3:cs3 gpio2:cs2 gpio1:cs1 gpio0:cs0 gnd (x2) gnd2 (x2) gnd1 mdata [4:1] mflag [4:1] tck tms tdi tdo reset trst feb ?04 ds612f1
cs5376a 2 table of contents 1. general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. digital filter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2. integrated peripheral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3. system level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.4. configuration interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. characteristics and specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 specified operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3. system design with cs5376a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2. reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3. clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4. synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.5. system configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.6. digital filter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.7. data collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.8. integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4. power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.2. bypass capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3. power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5. reset control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.2. reset self-tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.3. boot configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6. clock generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.2. synchronous clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3. master clock jitter and skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7. synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.2. msync generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.3. digital filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.4. modulator synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.5. test bit stream synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8. configuration by eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8.2. eeprom hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8.3. eeprom organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8.4. eeprom configuration commands . . . . . . . . . . . . . . . . . . . . . . . . . . .28 8.5. example eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. configuration by microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
cs5376a 3 9.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 9.2. microcontroller hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 9.3. microcontroller serial transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 9.4. microcontroller configuration commands . . . . . . . . . . . . . . . . . . . . . . .35 9.5. example microcontroller configuration . . . . . . . . . . . . . . . . . . . . . . . . .37 10. modulator interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 10.2. modulator clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 10.3. modulator synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 10.4. modulator data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 10.5. modulator flag inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 11. digital filter initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1. filter coefficient selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 11.2. filter configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 12. sinc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.1. sinc1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 12.2. sinc2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 12.3. sinc3 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 12.4. sinc filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 13. fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1. fir1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 13.2. fir2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 13.3. on-chip fir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 13.4. programmable fir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 13.5. fir filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 14. iir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.1. iir architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 14.2. iir1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 14.3. iir2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 14.4. iir3 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 14.5. on-chip iir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 14.6. programmable iir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 14.7. iir filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15. gain and offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1. gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 15.2. offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 15.3. offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 16. serial data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.2. sd port data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.3. sd port transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17. test bit stream generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.2. tbs architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.3. tbs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.4. tbs data source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 17.5. tbs sine wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 17.6. tbs impulse output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
cs5376a 4 17.7. tbs loopback testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 17.8. tbs synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 18. time break controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 18.2. time break operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 18.3. time break delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 19. general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 19.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 19.2. gpio architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 19.3. gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 19.4. gpio input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 19.5. gpio output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 20. serial peripheral interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 20.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 20.2. spi 2 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 20.3. spi 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 20.4. spi 2 transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 21. boundary scan jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 21.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 21.2. jtag architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 22. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 22.1. changes from cs5376 rev a to cs5376 rev b . . . . . . . . . . . . . . . . . .79 22.2. changes from cs5376 rev b to cs5376a rev a . . . . . . . . . . . . . . . . .79 23. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 23.1. spi 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 23.2. digital filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 24. pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 25. package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26. document revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 list of figures figure 1. cs5376a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2. digital filtering stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3. fir and iir coefficient set selection word. . . . . . . . . . . . . . . . . . . . .11 figure 4. mosi write timing in spi slave mode . . . . . . . . . . . . . . . . . . . . . . . .15 figure 5. miso read timing in spi slave mode . . . . . . . . . . . . . . . . . . . . . . . .15 figure 6. sd port read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 7. sync, mclk, msync, mdata interface timing . . . . . . . . . . . . . . .17 figure 8. tbs output clock and data timing. . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9. multi-channel system block diagram . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10. power supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 11. reset control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 12. clock generation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 13. synchronization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 14. eeprom configuration block diagram . . . . . . . . . . . . . . . . . . . . . .26
cs5376a 5 figure 15. spi 1 eeprom read transactions . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 16. 8 kbyte eeprom memory organization. . . . . . . . . . . . . . . . . . . . . .28 figure 17. serial peripheral interface 1 (spi 1) block diagram . . . . . . . . . . . . .32 figure 18. microcontroller serial transactions . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 19. spi 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 20. modulator data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 21. digital filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 22. fir and iir coefficient set selection word. . . . . . . . . . . . . . . . . . . .42 figure 23. sinc filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 24. sinc filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 25. fir filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 26. fir filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 27. fir1 coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 28. fir2 linear phase coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 29. fir2 minimum phase coefficients . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 30. iir filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 31. iir filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 32. gain and offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 33. serial data port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 34. sd port data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 35. sd port transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 36. test bit stream generator block diagram . . . . . . . . . . . . . . . . . . . .64 figure 37. time break block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 38. gpio bi-directional structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 39. serial peripheral interface 2 (spi 2) block diagram . . . . . . . . . . . . .71 figure 40. spi 2 master mode transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 41. spi 2 transaction details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 42. jtag block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 43. spi 1 control register spi1ctrl. . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 44. spi 1 command register spi1cmd . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 45. spi 1 data register spi1dat1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 46. spi 1 data register spi1dat2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 47. hardware configuration register config . . . . . . . . . . . . . . . . . . . .88 figure 48. gpio configuration register gpcfg0 . . . . . . . . . . . . . . . . . . . . . . .89 figure 49. gpio configuration register gpcfg1 . . . . . . . . . . . . . . . . . . . . . . .90 figure 50. spi 2 control register spi2ctrl. . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 51. spi 2 command register spi2cmd . . . . . . . . . . . . . . . . . . . . . . . . .92 figure 52. spi 2 data register spi2dat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 53. filter configuration register filtcfg . . . . . . . . . . . . . . . . . . . . . . .94 figure 54. gain correction register gain1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 55. offset correction register offset1 . . . . . . . . . . . . . . . . . . . . . . . .96 figure 56. time break counter register timebrk . . . . . . . . . . . . . . . . . . . . . .97 figure 57. test bit stream configuration register tbscfg . . . . . . . . . . . . . . .98 figure 58. test bit stream gain register tbsgain . . . . . . . . . . . . . . . . . . . . .99 figure 59. user defined system register system1. . . . . . . . . . . . . . . . . . . .100 figure 60. hardware version id register version . . . . . . . . . . . . . . . . . . . .101 figure 61. self test result register selftest . . . . . . . . . . . . . . . . . . . . . . .102
cs5376a 6 list of tables table 1. microcontroller and eeprom configuration commands . . . . . . . . . . .10 table 2. tbs configurations using on-chip data . . . . . . . . . . . . . . . . . . . . . . .11 table 3. spi 1 and digital filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4. maximum eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 5. eeprom boot configuration commands . . . . . . . . . . . . . . . . . . . . . .29 table 6. example eeprom file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7. microcontroller boot configuration commands . . . . . . . . . . . . . . . . . .35 table 8. example microcontroller configuration . . . . . . . . . . . . . . . . . . . . . . . . .38 table 9. sinc filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 10. sinc1 and sinc2 filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . .45 table 11. sinc3 filter coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 12. fir filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 13. sinc + fir group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 14. minimum phase group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 14. iir filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 15. iir filter coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 16. tbs configurations using on-chip data . . . . . . . . . . . . . . . . . . . . . .65 table 17. tbs impulse characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 18. jtag instructions and idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 19. jtag scan cell mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
cs5376a 7 1. general description the cs5376a is a multi-channel digital filter with integrated system peripherals. figure 1 illustrates a simplified block diagram of the cs5376a. 1.1 digital filter features ? multi-channel decimation filter for cs5371/72 ? modulators. - 1, 2, 3, or 4 channel concurrent operation. synchronous operation for simultaneous sam- pling in multi-sensor systems. - internal synchronization of digital filter phase to an external sync signal. multiple output word rates, including low bandwidth rates. - standard output rates: 4000, 2000, 1000, 500, 333, 250 sps. - low bandwidth rates: 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 sps. flexible digital filter configuration. (see figure 2) - cascaded sinc, fir, and iir filters with selectable output stage. - linear and minimum phase fir low-pass filter coefficients included. - 3 hz butterworth iir high-pass filter coef- ficients included. - fir and iir coefficients are programmable to create a custom filter response. digital gain correction. - individual channel gain correction to nor- malize signal amplitudes. figure 1. cs5376a block diagram sck1 serial data output port decimation and filtering engine modulator data interface test bit stream controller clock and synchronization tbsclk tbsdata spi 1 serial peripheral interface 1 jtag interface time break controller spi 2 serial peripheral interface 2 gpio general purpose i/o sdclk sddat sdtki boot vd (x2) vdd1 vdd2 (x2) sync clk mclk msync timeb miso mosi ssi sint sdrdy sck2 so si1 si2 si3 si4 gpio11:eecs gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4:cs4 gpio3:cs3 gpio2:cs2 gpio1:cs1 gpio0:cs0 gnd (x2) gnd2 (x2) gnd1 mdata [4:1] mflag [4:1] tck tms tdi tdo reset trst
cs5376a 8 digital offset correction and calibration. - individual channel offset correction to re- move measurement offsets. - calibration engine for automatic calcula- tion of offset correction factors. 1.2 integrated peripheral features synchronous operation for simultaneous sam- pling in multi-sensor systems. - mclk / msync output signals to syn- chronize external components. high speed serial data output port (sd port). - asynchronous operation to 4 mhz for di- rect connection to system telemetry. - internal 8-deep data fifo for flexible out- put timing. digital test bit stream signal generator suitable for cs4373 ? test dac. - sine wave output mode for testing total har- monic distortion. - impulse output mode for transfer function characterization. - programmable waveform data for custom test signal generation. time break controller to record system timing information. - dedicated tb status bit in the output data stream. - programmable output delay to match sys- tem group delay. additional hardware peripherals simplify sys- tem design. - 12 general purpose i/o (gpio) pins for lo- cal hardware control. - secondary spi 2 serial port to control local serial peripherals. - jtag port for boundary scan (ieee 1149.1 compliant). 1.3 system level features flexible configuration options. - configuration 'on-the-fly' via microcontrol- ler or system telemetry. - fixed configuration via stand-alone boot figure 2. digital filtering stages sinc filter 2 - 64000 fir1 4 fir2 2 iir1 iir2 1 st order 2 nd order output to high speed serial data port dc offset corrections output word rate from 4000 sps ~ 1 sps gain & modulator 512 khz input
cs5376a 9 eeprom. low power consumption. - 37 mw for 4-channel operation at 500 sps (9.25 mw/channel). -40 w standby mode. flexible power supply configurations. - separate digital logic core, telemetry i/o, and modulator i/o power supplies. - telemetry i/o and modulator i/o interfaces operate from 3.3 v or 5 v. - digital logic core operates from 3.0 v, 3.3 v or 5 v. small 64-pin tqfp package. - total footprint 12 mm x 12 mm plus five bypass capacitors. 1.4 configuration interface configuration from microcontroller or stand- alone boot eeprom. - microcontroller boot permits reconfigura- tion during operation. - eeprom boot sets a fixed operational con- figuration. configuration commands written through seri- al peripheral interface 1. (see table 1) - standardized microcontroller interface us- ing spi 1 registers. (see table 3) - commands write digital filter registers, fil- ter coefficients, and test bit stream data. - digital filter registers set hardware config- uration options.
cs5376a 10 microcontroller boot configuration commands eeprom boot configuration commands [data] indicates data word returned from digital filter. (data) indicates multiple words of this type are to be written. name cmd 24-bit dat1 24-bit dat2 24-bit description nop 000000 - - no operation write df register 000001 reg data write digital filter register read df register 000002 reg [data] - - read digital filter register write fir coefficients 000003 num fir1 (fir coef) num fir2 (fir coef) write custom fir coefficients write iir coefficients 000004 a11 b11 a22 b21 b10 a21 b20 b22 write custom iir coefficients write rom coefficients 000005 coef sel - use on-chip coefficients write tbs data 000006 num tbs (tbs data) - (tbs data) write custom test bit stream data write rom tbs 000007 - - use on-chip tbs data filter start 000008 - - start digital filter operation filter stop 000009 - - stop digital filter operation name cmd 8-bit data 24-bit description nop 00 - no operation write df register 01 reg data write digital filter register write fir coefficients 02 num fir1 num fir2 (fir coef) write custom fir coefficients write iir coefficients 03 a11 b10 b11 a21 a22 b20 b21 b22 write custom iir coefficients write rom coefficients 04 coef sel use on-chip coefficients write tbs data 05 num tbs (tbs data) write custom test bit stream data write rom tbs 06 - use on-chip tbs data filter start 07 - start digital filter operation table 1. microcontroller and eeprom configuration commands
cs5376a 11 bits 23:20 19:16 15:12 11:8 7:4 3:0 selection 0000 0000 iir2 iir1 fir2 fir1 figure 3. fir and iir coefficient set selection word bits 15:12 iir2 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 11:8 iir1 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 7:4 fir2 coefficients 0000 linear phase 0001 minimum phase bits 3:0 fir1 coefficients 0000 linear phase 0001 minimum phase test bit stream characteristic equation: (signal freq) * (# tbs data) * (interpolation + 1) = output rate example: (31.25 hz) * (1024) * (0x07 + 1) = 256 khz signal frequency (tbsdata) output rate (tbsclk) output rate selection (rate) interpolation selection (intp) 10.00 hz 256 khz 0x4 0x18 10.00 hz 512 khz 0x5 0x31 25.00 hz 256 khz 0x4 0x09 25.00 hz 512 khz 0x5 0x13 31.25 hz 256 khz 0x4 0x07 31.25 hz 512 khz 0x5 0x0f 50.00 hz 256 khz 0x4 0x04 50.00 hz 512 khz 0x5 0x09 125.00 hz 256 khz 0x4 0x01 125.00 hz 512 khz 0x5 0x03 table 2. tbs configurations using on-chip data
cs5376a 12 spi 1 registers digital filter registers name addr. type # bits description spi1ctrl 00 - 02 r/w 8, 8, 8 spi 1 control spi1cmd 03 - 05 r/w 8, 8, 8 spi 1 command spi1dat1 06 - 08 r/w 8, 8, 8 spi 1 data 1 spi1dat2 09 - 0b r/w 8, 8, 8 spi 1 data 2 name addr. type # bits description config 00 r/w 24 hardware configuration reserved 01-0d r/w 24 reserved gpcfg0 0e r/w 24 gpio[7:0] direction, pull-up enable, and data gpcfg1 0f r/w 24 gpio[11:8] direction, pull-up enable, and data spi2ctrl 10 r/w 24 spi 2 control spi2cmd 11 r/w 16 spi 2 command spi2dat 12 r/w 24 spi 2 data reserved 13-1f r/w 24 reserved filtcfg 20 r/w 24 digital filter configuration gain1 21 r/w 24 gain correction channel 1 gain2 22 r/w 24 gain correction channel 2 gain3 23 r/w 24 gain correction channel 3 gain4 24 r/w 24 gain correction channel 4 offset1 25 r/w 24 offset correction channel 1 offset2 26 r/w 24 offset correction channel 2 offset3 27 r/w 24 offset correction channel 3 offset4 28 r/w 24 offset correction channel 4 timebrk 29 r/w 24 time break delay tbscfg 2a r/w 24 test bit stream configuration tbsgain 2b r/w 24 test bit stream gain system1 2c r/w 24 user defined system register 1 system2 2d r/w 24 user defined system register 2 version 2e r/w 24 hardware version id selftest 2f r/w 24 self-test result code table 3. spi 1 and digital filter registers
cs5376a 13 2. characteristics and specifications min / max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are derived from measurements taken at nomi- nal supply voltages and t a = 25 c. gnd, gnd1, gnd2 = 0 v, all voltages with respect to 0 v. specified operating conditions absolute maximum ratings 1. transient currents up to 100 ma will not cause scr latch-up. parameter symbol min nom max unit logic core power supply vd 2.85 3.0 5.25 v microcontroller interface power supply vdd1 3.135 3.3 5.25 v modulator interface power supply vdd2 3.135 3.3 5.25 v ambient operating temperature industrial (-iq) t a -40 - 85 c parameter symbol min max units dc power supplies logic core microcontroller interface modulator interface vd vdd1 vdd2 -0.3 -0.3 -0.3 6.0 6.0 6.0 v v v input current, any pin except supplies (note 1) i in -10ma input current, power supplies (note 1) i in -50ma output current (note 1) i out -25ma power dissipation p dn - 500 mw digital input voltages v ind -0.3 vdd+0.3 v ambient operating temperature (power applied) t a -40 85 c storage temperature range t stg -65 150 c
cs5376a 14 thermal characteristics digital characteristics notes: 2. max leakage for pins with pull-up resistors (trst , tms, tdi, ssi , gpio, mosi, sck1) is 250 a. power consumption parameter symbol min typ max unit allowable junction temperature t j --135c junction to ambient thermal impedance ja -65 c / w ambient operating temperature (power applied) t a -40 - +85 c parameter symbol min typ max unit high-level input drive voltage v ih 0.6 * vdd - vdd v low-level input drive voltage v il 0.0 - 0.8 v high-level output drive voltage i out = -40 a v oh vdd - 0.3 - vdd v low-level output drive voltage i out = +40 a v ol 0.0 - 0.3 v rise times, digital inputs t rise - - 100 ns fall times, digital inputs t fall - - 100 ns rise times, digital outputs t rise - - 100 ns fall times, digital outputs t fall - - 100 ns input leakage current (note 2) i in - 1 10a 3-state leakage current i oz -- 10a digital input capacitance c in -9-pf digital output pin capacitance c out -9-pf parameter symbol min typ max unit operational power consumption 1.024 mhz digital filter clock pwr 1 -21-mw 2.048 mhz digital filter clock pwr 2 -26-mw 4.096 mhz digital filter clock pwr 4 -37-mw 8.192 mhz digital filter clock pwr 8 -57-mw 16.384 mhz digital filter clock pwr 16 -85-mw standby power consumption 32 khz digital filter clock, filter stopped pwr s -40-w 2.6 v 0.7 v t fallin t risein 4.6 v 0.4 v t riseout t fallout 0.90 * vdd 0.10 * vdd 0.90 * vdd 0.10 * vdd
cs5376a 15 switching characteristics spi 1 interface timing (external master) parameter symbol min typ max unit mosi write timing ssi enable to valid latch clock t 1 60 - - ns data set-up time prior to sck1 rising t 2 60 - - ns data hold time after sck1 rising t 3 120 - - ns sck1 high time t 4 120 - - ns sck1 low time t 5 120 - - ns sck1 falling prior to ssi disable t 6 60 - - ns miso read timing sck1 falling to new data bit t 7 - - 200 ns sck1 high time t 8 120 - - ns sck1 low time t 9 120 - - ns ssi rising to miso hi-z t 10 - - 150 ns figure 4. mosi write timing in spi slave mode ssi mosi sclk msb msb - 1 lsb t 6 t 5 t 4 t 3 t 2 t 1 sck1 figure 5. miso read timing in spi slave mode miso sclk msb msb - 1 lsb t 10 t 9 t 8 t 7 ssi sck1
cs5376a 16 switching characteristics serial data port (sd port) parameter symbol min typ max unit sdtki to sdrdy falling edge t 1 60 - - ns sdtki high time width t 2 60 - 1000 ns sdrdy falling edge to sdclk falling edge t 3 50 - - ns data setup time prior to sdclk rising t 4 60 - - ns data hold time after sdclk rising t 5 60 - - ns sdclk high time t 6 120 - - ns sdclk low time t 7 120 - - ns sdclk rising to sdrdy rising t 8 60 - - ns data hold time after sdrdy rising t 9 - - 150 ns sdrdy high to sdtko rising edge t 10 --60ns sdtko high time t 11 90 - - ns figure 6. sd port read timing sdtki sddat sdclk t 1 t 6 sdrdy t 7 t 4 t 5 sdtko t 3 t 8 t 2 t 9 t 10 t 11
cs5376a 17 switching characteristics clk, sync, mclk, msync, and mdatax notes: 3. master clock frequencies above or below 32.768 mhz will affect generated clock frequencies. 4. sampling synchronization between multiple cs5376a devices receiving identical sync signals. parameter symbol min typ max unit master clock frequency (note 3) clk 32 32.768 33 mhz master clock duty cycle dty 40 - 60 % master clock rise time t rise --20ns master clock fall time t fall --20ns master clock jitter jtr - - 300 ps synchronization after sync rising (note 4) sync -2 - 2 s msync setup time to mclk rising t msr 20 - - ns mclk rising to valid mdata t mdv --75ns msync falling to mclk rising t msf 20 - - ns msync mclk mdatax figure 7. sync, mclk, msync, mdata interface timing t msd t msd t msh data1 data2 sync f mclk 2.048 mhz 1.024 mhz t msd = t mclk / 4 t msd = 122 ns t msd = 244 ns t msh = t mclk t msh = 488 ns t msh = 976 ns note: sync input latched on mclk rising edge. msync output triggered by mclk falling edge.
cs5376a 18 switching characteristics test bit stream (tbs) 5. tbsclk phase can be delayed in 1/8 increments. the timing diagram shows no tbsclk delay. 6. tbsdata can be delayed from 0 to 63 full bit periods. the timing diagram shows no tbsdata delay. parameter symbol min typ max unit tbs clock timing tbs clock period t 1 - 3.906 - s tbs clock high time (note 5) t 2 40 - 60 % tbs clock low time t 3 40 - 60 % tbs data output timing tbs data bit rate - 256 - kbps tbs data rising to tbs clock rising setup time t 4 60 - - ns tbs clock rising to tbs data falling hold time (note 6) t 5 60 - - ns figure 8. tbs output clock and data timing tbsclk tbsdata mclk t 1 t 2 t 3 t 5 t 4 note: example timing shown for a 256 khz output rate and no programmable delays.
cs5376a 19 3. system design with cs5376a figure 9 illustrates a simplified block diagram of the cs5376a in a multi-channel measurement sys- tem. up to four differential sensors are connected through cs3301/02 differential amplifiers to the cs5371/72 ? modulators, where analog to digital conversion occurs. each modulators 1-bit output connects to a cs5376a mdata input, where the oversampled ? data is decimated and filtered to 24-bit output samples at a programmed output rate. these output samples are buffered in an 8-deep data fifo and passed to the system telemetry on command. system self tests are performed by connecting the cs5376a test bit stream (tbs) generator to the cs4373 test dac. analog tests drive differential signals from the cs4373 test dac into the multi- plexed inputs of the cs3301/02 amplifiers or di- rectly to the sensors through external analog switches. digital loopback tests internally connect the tbs digital output directly to the cs5376a modulator inputs. 3.1 power supplies the multi-channel system shown in figure 9 typi- cally operates from a 2.5 v or 5 v analog power supply and a 3.3 v digital power supply. the cs5376a logic core can be powered from 3 v to minimize power consumption, if required. 3.2 reset control system reset is required only for the cs5376a de- vice, and is a standard active low signal that can be generated by a power supply monitor or microcon- troller. other system devices default to a power- down state when the cs5376a is reset. figure 9. multi-channel system block diagram ? modulator ? modulator digital filter amp amp amp amp geophone or hydrophone sensor geophone or hydrophone sensor geophone or hydrophone sensor geophone or hydrophone sensor m u x m u x m u x m u x test dac controller or configuration eeprom communication interface cs3301 cs3302 cs5371 cs5371 cs5376a cs4373 system telemetry cs3301 cs3302 cs3301 cs3302 cs3301 cs3302 cs5372 cs5372
cs5376a 20 3.3 clock generation a single 32.768 mhz low-jitter clock input, which can be generated from a vcxo based pll, is re- quired to drive the cs5376a device. clock inputs for other system devices are driven by clock out- puts from the cs5376a. 3.4 synchronization digital filter phase and analog sample timing of the four ? modulators connected to the cs5376a are synchronized by a rising edge on the sync pin. if a synchronization signal is received identically by all cs5376a devices in a measurement network, synchronous sampling across the network is guar- anteed. 3.5 system configuration through the spi 1 serial port, filter coefficients and digital filter register settings can either be pro- grammed by a microcontroller or automatically loaded from an external eeprom after reset. sys- tem configuration is only required for the cs5376a device, as other devices are configured via the cs5376a general purpose i/o pins. two registers in the digital filter, system1 and system2 (0x2c, 0x2d), are provided for user de- fined system information. these are general pur- pose registers that will hold any 24-bit data values written to them. 3.6 digital filter operation after analog to digital conversion occurs in the modulators, the oversampled 1-bit ? data is read into the cs5376a through the mdata pins. the digital filter then processes data through the en- abled filter stages, decimating it to 24-bit words at a programmed output word rate. the final 24-bit samples are concatenated with 8-bit status words and placed into an output fifo. 3.7 data collection data is collected from the cs5376a through the serial data port (sd port). automatically or upon request, depending how the sdtki pin is connect- ed, the sd port initiates serial transactions to trans- fer 32-bit data from the output fifo to the system telemetry. the output fifo has eight data locations to permit latency in data collection. 3.8 integrated peripherals test bit stream (tbs) a digital signal generator built into the cs5376a produces a 1-bit ? sine wave or impulse function. this digital test bit stream can be connected to the cs4373 test dac to create high quality analog test signals or it can be internally looped back to the cs5376a mdata inputs to test the digital filter and data collection circuitry. time break timing information is recorded during data collec- tion by strobing the timeb pin. a dedicated flag in the sample status bits, tb, is set high to indicate over which measurement the timing event oc- curred. general purpose i/o (gpio) twelve general purpose pins are available on the cs5376a for system control. each pin can be set as input or output, high or low, with an internal pull- up enabled or disabled. the cs3301/02, cs5371/72 and cs4373 devices in figure 9 are configured by simple pin settings controlled through the cs5376a gpio pins. serial peripheral interface 2 (spi 2) a secondary master mode serial port to communi- cate with external serial peripherals. jtag port boundary scan jtag is ieee 1149.1 compliant.
cs5376a 21 4. power supplies the cs5376a has three sets of power supply in- puts. two sets supply power to the i/o pins of the device (vdd1, vdd2), and the third supplies power to the logic core (vd). the i/o pin power supplies determine the maximum input and output voltages when interfacing to peripherals, and the logic core power supply largely determines the power consumption of the cs5376a. 4.1 pin descriptions vdd1, gnd1 - pins 54,53 sets the interface voltage to a microcontroller and system telemetry. can be driven with voltages from 3.3 v to 5 v. vdd1 powers pins 1-5 and 41-64: trst , tms, tck, tdi, tdo gpio6 - gpio11:eecs sso , sck1, ssi , miso, mosi, sint , reset , boot, timeb, clk, sync sddat, sdrdy , sdclk, sdtko, sdtki vdd2, gnd2 - pins 11, 25, 24, 38 sets the interface voltage to the modulators, test dac, and serial peripherals. can be driven with voltages from 3.3 v to 5 v. vdd2 powers pins 8-37: tbsclk, tbsdata mclk/2, mclk, msync mdata1 - mdata4 mflag1 - mflag4 si1 - si4, so, sck2 gpio0:cs0 - gpio5 trst tms tck tdi tdo gnd vd tbsclk tbsdata dnc vdd2 mclk/2 mclk msync mdata4 mflag4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 mdata3 mflag3 mdata2 mflag2 mdata1 mflag1 gnd gnd2 vdd2 si4 si3 si2 si1 so sck2 gpio0:cs0 sdtki sdtko sdclk sdrdy sddat sync clk timeb boot reset vdd1 gnd1 sint mosi miso ssi cs5376a vdd1 pad ring vdd2 pad ring vd pad ring sck1 sso gpio11:eecs gpio10 gpio9 gpio8 gpio7 gpio6 vd gnd gnd2 gpio5 gpio4:cs4 gpio3:cs3 gpio2:cs2 gpio1:cs1 vd pad ring figure 10. power supply block diagram
cs5376a 22 vd, gnd - pins 7, 40, 6, 23, 39 sets the operational volta ge of the cs5376a logic core. can be driven with voltages from 3 v to 5 v. a 3 v supply minimizes total power consumption. 4.2 bypass capacitors each power supply pin should be bypassed with parallel 1 f and 0.01 f caps, or by a single 0.1 f cap, placed as close as possible to the cs5376a. bypass capacitors should be ceramic (x7r, c0g), tantalum, or other good quality di- electric type. 4.3 power consumption power consumption of the cs5376a depends pri- marily on the power supply voltage of the logic core (vd) and the programmed digital filter clock rate. digital filter clock rates are selected based on the required output word rate as explained in ?dig- ital filter initialization? on page 41.
cs5376a 23 5. reset control the cs5376a reset signal is active low. when re- leased, a series of self-tests are performed and the device either actively boots from an external ee- prom or enters an idle state waiting for microcon- troller configuration. 5.1 pin descriptions reset - pin 55 reset input, active low. boot - pin 56 boot mode select, latched following a reset ris- ing edge. boot = 1 = eeprom boot boot = 0 = microcontroller boot 5.2 reset self-tests after reset is released but before booting, a se- ries of digital filter self-tests are run. results are combined into the selftest register (0x2f), with 0x0aaaaa indicating all passed. self-tests require 60 ms to complete, after which configura- tion commands are serviced. 5.3 boot configurations the logic state of the boot pin after reset deter- mines if the cs5376a actively reads configuration information from eeprom or enters an idle state waiting for a microcontroller to write configuration commands. eeprom boot when the boot pin is high after reset, the cs5376a actively reads data from an external seri- al eeprom and then begins operation in the spec- ified configuration. configuration commands and data are encoded in the eeprom as specified in the ?configuration by eeprom? section of this data sheet, starting on page 26. microcontroller boot when the boot pin is low after reset, the cs5376a enters an idle state waiting for a micro- controller to write conf iguration commands and initialize filter operation. configuration commands and data are written as specified in the ?configura- tion by microcontroller? section of this data sheet, starting on page 32. reset self-tests selftest register boot pin eeprom boot controller boot 1 0 figure 11. reset control block diagram self-test type pass code fail code program rom 0x00000a 0x00000f data rom 0x0000a0 0x0000f0 program ram 0x000a00 0x000f00 data ram 0x00a000 0x00f000 execution unit 0x0a0000 0x0f0000
cs5376a 24 6. clock generation the cs5376a requires a 32.768 mhz master clock input, which is used to gene rate internal digital fil- ter clocks and external modulator clocks. 6.1 pin description clk - pin 58 clock input, nominal frequency 32.768 mhz. 6.2 synchronous clocking to guarantee synchronous measurements through- out a sensor network, the cs5376a master clock should be distributed to arrive at all nodes in phase. the 32.768 mhz master clock can either be direct- ly distributed through the system telemetry, or re- constructed locally using a vcxo based pll. to ensure recovered clocks have identical phase, sys- tem pll designs should use a phase/frequency de- tector architecture. 6.3 master clock jitter and skew care must be taken to minimize jitter and skew in the received master clock as both parameters affect measurement performance. jitter in the master clock causes jitter in the gener- ated modulator clocks, resulting in sample timing errors and increased noise. skew in the master clock from node to node creates a sample timing offset, resulting in systematic mea- surement errors in the reconstructed signal. clock divider clk dspcfg register mclk internal clocks figure 12. clock generation block diagram and generator mclk output
cs5376a 25 7. synchronization the cs5376a has a dedicated sync input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator an- alog sampling. by providing simultaneous rising edges to the sync pins of multiple cs5376a de- vices, synchronous sampling across a network can be guaranteed. 7.1 pin description sync - pin 59 synchronization input, rising edge triggered. 7.2 msync generation the sync signal rising edge is used to generate a retimed synchronization signal, msync. the msync signal reinitializes internal digital filter phase and is driven onto the msync output pin to phase align modulator analog sampling. the msen bit in the digital filter config register (0x00) enables msync generation. see ?modula- tor interface? on page 39 for more information about msync. 7.3 digital filter synchronization the internal msync signal resets the digital filter state machine to establish a known digital filter phase. filter convolutions restart, and the next out- put word is available one full sample period later. repetitive synchronization is supported when sync events occur at exactly the selected output word rate. in this case, re-synchronization occurs at the start of a convolution cycle when the digital fil- ter state machine is already reset. 7.4 modulator synchronization the external msync signal phase aligns modula- tor analog sampling when connected to the cs5371/72 msync input. this ensures synchro- nous analog sampling relative to mclk. repetitive synchronization of the modulators is supported when sync events occur at exactly the selected output word rate. in this case, synchroni- zation will occur at the start of analog sampling. 7.5 test bit stream synchronization when the test bit stream generator is enabled, an msync signal can reset the internal data pointer. this restarts the test bit stream from the first data point to establish a known output signal phase. the tsync bit in the digital filter tbscfg regis- ter (0x2a) enables synchronization of the test bit stream by msync. when tsync is disabled, the test bit stream phase is not affected by msync. figure 13. synchronization block diagram sync msync digital filter generator msync 0 1 msen 0 1 tsync test bit stream output
cs5376a 26 8. configuration by eeprom after reset, the cs5376a reads the state of the boot pin to determine a source for configuration commands. if boot is high, the cs5376a ini- tiates serial transactions through the spi 1 port to read configuration information from an external eeprom. 8.1 pin descriptions pins required for eeprom boot are listed here, other spi 1 pins are inactive. gpio11:eecs - pin 46 eeprom chip select output, active low. sck1 - pin 48 serial clock output, nominally 1.024 mhz. mosi - pin 51 serial data output pin. valid on rising edge of sck1, transition on falling edge. miso - pin 50 serial data input pin. valid on rising edge of sck1, transition on falling edge. 8.2 eeprom hardware interface when booting from eeprom the cs5376a spi 1 port actively performs serial transactions, as shown in figure 15, to read configuration commands and data. 8-bit spi opcodes a nd 16-bit addresses are combined to read back 8-bit configuration com- mands and 24-bit configuration data. system design should include a connection to the configuration eeprom for in-circuit reprogram- ming. the cs5376a spi 1 pins tri-state when inac- tive to support external connections to the serial bus. 8.3 eeprom organization the boot eeprom holds the 8-bit commands and 24-bit data required to initialize the cs5376a into an operational state. configuration information starts at memory location 0x10, with addresses 0x00 to 0x0f free for use as manufacturing header information. the first serial transaction reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. command and data reads continue until the ?filter start? command is recognized. the maximum number of bytes that can be written for a single configuration is approximately gpio11:eecs sck1 miso mosi cs5376a at25640 cs sck si so 46 48 50 51 1 6 2 5 vd gnd wp vcc hold 387 4 figure 14. eeprom configuration block diagram
cs5376a 27 sck1 mosi eecs msb lsb miso x 61 2 3 4 5 msb lsb 61 2 3 4 5 18 27 6 5 4 3 cycle mosi miso ssi 0x03 addr data1 data3 data2 eecs read 1 byte / 3 byte addr cmd addr data 2 byte figure 15. spi 1 eeprom read transactions spi 1 read from eeprom instruction opcode address definition read 0x03 addr[15:0] read data beginning at the address given in addr.
cs5376a 28 5 kbyte (40 kbit), which includes command over- head: supported serial configuration eeproms are spi mode 0 (0,0) compatible, 16-bit addresses, 8- bit data, larger than 5 kbyte (40 kbit). atmel at25640, at25128, or similar serial eeproms are recommended. 8.4 eeprom configuration commands a summary of available eeprom commands is shown in table 5. write df register - 0x01 this eeprom command writes a data value to the specified digital filter register. digital filter regis- ters control hardware peripherals and filtering functions. see ?digital filter registers? on page 87 for the bit definitions of the digital filter registers. sample command: write digital filter regist er 0x00 with data value 0x070431. then write 0x20 with data 0x000240. 01 00 00 00 07 04 31 01 00 00 20 00 02 40 write fir coefficients - 0x02 this eeprom command writes custom coeffi- cients for the fir1 and fir2 filters. the first two data words set the number of fir1 and fir2 coef- ficients to be written. the remaining data words are the concatenated fir1 and fir2 coefficients. a maximum of 255 coefficients can be written for each fir filter, though the available digital filter computation cycles will limit their practical size. see ?fir filter? on page 47 for more information about fir filter coefficients. sample command: write fir1 coefficients 0x00022e, 0x000771 then fir2 coefficients 0xffffb9, 0xfffe8d. 02 00 00 02 00 00 02 00 02 2e 00 07 71 ff ff b9 ff fe 8d write iir coefficients - 0x03 this eeprom command writes custom coeffi- cients for the two stage iir filter. the iir architec- ture and number of coefficients is fixed, so eight data words containing coefficient values always immediately follow the command byte. the iir co- efficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. see ?iir filter? on page 55 for more information about iir filter coefficients. figure 16. 8 kbyte eeprom memory organization 0000h 1fffh eeprom manufacturing information eeprom command and data values mfg header 8-bit command 0010h n x 24-bit data 8-bit command n x 24-bit data . . . table 4. maximum eeprom configuration memory requirement bytes digital filter registers (22) 154 fir coefficients (255+255) 1537 iir coefficients (3+5) 25 test bit stream data (1024) 3076 ?filter start? command 1 total bytes 4793
cs5376a 29 sample command: write iir1 coefficients 0x84bc9d, 0x7da1b1, 0x825e4f, and iir2 coefficients 0x83694f, 0x3cad5f, 0x3e5104, 0x835df8, 0x3e5104. 03 84 bc 9d 7d a1 b1 82 5e 4f 83 69 4f 3c ad 5f 3e 51 04 83 5d f8 3e 51 04 write rom coefficients - 0x04 this eeprom command selects the on-chip coef- ficients for the fir1, fir2, iir 1st order, and iir 2nd order filters for use by the digital filter. one data word is required to select which internal coef- ficient sets to use. see ?filter coefficient selec- tion? on page 41 for information about selecting on-chip fir and iir coefficient sets. sample command: select iir1 and iir2 3 hz @ 500 sps low-cut co- efficients, with fir1 and fir2 linear phase high- cut coefficients. data word 0x002200. 04 00 22 00 write tbs data - 0x05 this eeprom command writes a custom data set for the test bit stream (tbs) generator. this com- mand, along with the ability to program the test bit stream generator interpol ation and clock rate, can create custom frequency test signals. the first data word sets the number of tbs data to be written and the remaining data words are the tbs data values. see ?test bit stream generator? on page 64 for information about using custom test bit stream data sets. table 5. eeprom boot configuration commands (data) indicates multiple words of this type are to be written. name cmd 8-bit data 24-bit description nop 00 - no operation write df register 01 reg data write digital filter register write fir coefficients 02 num fir1 num fir2 (fir coef) write custom fir coefficients write iir coefficients 03 a11 b10 b11 a21 a22 b20 b21 b22 write custom iir coefficients write rom coefficients 04 coef sel use on-chip coefficients write tbs data 05 num tbs (tbs data) write custom test bit stream data write rom tbs 06 - use on-chip tbs data filter start 07 - start digital filter operation
cs5376a 30 sample command: write test bit stream data 0x000000, 0x0007da, 0x000fb5, 0x00178f. 05 00 00 04 00 00 00 00 07 da 00 0f b5 00 17 8f write tbs rom data - 0x06 this eeprom command selects the on-chip test bit stream (tbs) data for use by the tbs generator. no data words are required for this eeprom com- mand. see ?test bit stream generator? on page 64 for more information about the on-chip test bit stream data set. sample command: 06 filter start - 0x07 this eeprom command initializes and starts the digital filter. measurement data becomes available one full sample period after this command is re- ceived. no data words are required for this ee- prom command. sample command: 07 8.5 example eeprom configuration table 6 shows an example eeprom file for a min- imal cs5376a configuration.
cs5376a 31 table 6. example eeprom file addr data description 00 00 mfg header 01 00 02 00 03 00 04 00 05 00 06 00 07 00 08 00 09 00 0a 00 0b 00 0c 00 0d 00 0e 00 0f 00 10 04 write rom coefficients 11 00 12 22 13 00 14 06 write tbs rom data 15 01 write config register 16 00 17 00 18 00 19 07 1a 04 1b 31 1c 01 write filtcfg register 1d 00 1e 00 1f 20 addr data description 20 00 21 02 22 40 23 01 write tbscfg register 24 00 25 00 26 2a 27 07 28 40 29 40 2a 01 write tbsgain register 2b 00 2c 00 2d 2b 2e 04 2f b0 30 00 31 07 filter start
cs5376a 32 9. configuration by microcontroller after reset, the cs5376a reads the state of the boot pin to determine a source for configuration commands. if boot is low, the cs5376a receives configuration commands from a microcontroller. 9.1 pin descriptions pins required for microcontroller boot are listed here, other spi 1 pins are inactive. ssi - pin 49 slave select input pin, active low. serial chip select input from a microcontroller. sck1 - pin 48 serial clock input pin. serial clock input from mi- crocontroller, maximum 4.096 mhz. mosi - pin 51 serial data input pin. valid on rising edge of sck1, transition on falling edge. miso - pin 50 serial data output pin. valid on rising edge of sck1, transition on falling edge. open drain out- put requiring a 10 k ? pull-up resistor. sint - pin 52 serial interrupt output pin, active low. 1 us active low pulse output when ready for next serial trans- action. 9.2 microcontroller hardware interface when booting from a microcontroller the cs5376a spi 1 port receives configuration com- mands and configuration data through serial trans- actions, as shown in figure 18. 8-bit spi opcodes and 8-bit addresses are combined to read and write 24-bit configuration commands and data. microcontroller serial transactions require toggling the ssi pin as the cs5376a chip select and writing a serial clock to the sck1 input. serial data is input to the cs5376a on the mosi pin, and output from the cs5376a on the miso pin. 9.3 microcontroller serial transactions microcontroller configuration commands are writ- ten to the digital filter through the spi 1 registers. a 24-bit command and two 24-bit data words can be written to the spi 1 registers in any single serial transaction. some commands require additional data words through additional serial transactions to complete. 9.3.1 spi opcodes a microcontroller communicates with the cs5376a spi 1 port using standard 8-bit spi op- codes and an 8-bit spi address. the standard spi ?read? and ?write? opcodes are listed in figure 18. sck1 miso mosi pin logic spi 1 figure 17. serial peripheral interface 1 (spi 1) block diagram sint command ssi registers digital filter interpreter spi 1
cs5376a 33 sck1 mosi figure 18. microcontroller serial transactions ssi msb lsb miso x 61 2 3 4 5 msb lsb 61 2 3 4 5 18 27 6 5 4 3 cycle mosi 0x02 addr data1 miso mosi miso microcontroller write to spi 1 microcontroller read from spi 1 datan data2 ssi ssi 0x03 addr data1 datan data2 instruction opcode address definition write 0x02 addr[7:0] write spi 1 registers beginning at the address in addr. read 0x03 addr[7:0] read spi 1 registers beginning at the address in addr.
cs5376a 34 9.3.2 spi 1 registers the spi 1 registers are shown in figure 19 and are 24-bit registers mapped into an 8-bit register space as high, mid, and low bytes. see ?spi 1 registers? on page 82 for the bit definitions of the spi 1 reg- isters. 9.3.3 spi 1 transactions a serial transaction to the spi 1 registers starts with an spi opcode, followed by an address, and then some number of data bytes written or read starting at that address. typical serial write transactions require sending groups of 5, 8, or 11 total bytes to the spi1cmd or spi1dat1 registers. example 5-byte write transaction to spi1cmd 02 03 12 34 56 example 5-byte write transaction to spi1dat1 02 06 12 34 56 example 8-byte write transaction to spi1cmd 02 03 12 34 56 ab cd ef example 8-byte write transaction to spi1dat1 02 06 12 34 56 ab cd ef example 11-byte write transaction to spi1cmd 02 03 12 34 56 ab cd ef 65 43 21 typical serial read transactions require groups of 3 or 5 bytes, split between writing into mosi and reading from miso. 3-byte read transaction of mid-byte of spi1ctrl mosi: 03 01 00 miso: xx xx 12 5-byte read transaction of spi1dat1 mosi: 03 06 00 00 00 miso: xx xx 12 34 56 9.3.4 multiple serial transactions some configuration commands require multiple se- rial transactions to complete. there must be a small delay between transactions for the cs5376a to process the incoming data. three methods can be used to ensure the cs5376a is ready to receive the next configuration command. 1) delay a fixed 1 ms period to guarantee enough time for the command to be completed. 2) monitor the sint pin for a 1 us active low pulse. this pulse output occurs once the cs5376a com- pletes processing the current command. 3) verify the status of the e2dreq bit by reading the spi1ctrl register. when low, the cs5376a is ready for the next command. 9.3.5 polling e2dreq one transaction type that can always be performed no matter the delay from the previous configuration command is reading e2dreq in the mid-byte of the spi1ctrl register. a 3-byte read transaction. mosi: 03 01 00 miso: xx xx 01 <- e2dreq bit high miso: xx xx 00 <- e2dreq bit low name addr. type # bits description spi1ctrl 00 - 02 r/w 8, 8, 8 spi 1 control spi1cmd 03 - 05 r/w 8, 8, 8 spi 1 command spi1dat1 06 - 08 r/w 8, 8, 8 spi 1 data 1 spi1dat2 09 - 0b r/w 8, 8, 8 spi 1 data 2 figure 19. spi 1 registers
cs5376a 35 the e2dreq bit reads high while a configuration command is being processed. when low, the digital filter is ready to receive a new configuration com- mand. 9.4 microcontroller configuration commands a summary of available microcontroller configura- tion commands is listed in table 7. write df register - 0x01 this configuration command writes a specified digital filter register. digital filter registers control hardware peripherals and filtering functions. see ?digital filter registers? on page 87 for the bit def- initions of the digital filter registers. sample command: write digital filter regist er 0x00 with data value 0x070431. then write 0x20 with data 0x000240. 02 03 00 00 01 00 00 00 07 04 31 delay 1 ms, monitor sint , or poll e2dreq 02 03 00 00 01 00 00 20 00 02 40 delay 1 ms, monitor sint , or poll e2dreq read df register - 0x02 this command reads a specified digital filter regis- ter. the register value is requested in the first spi transaction, with the register value copied to spi1dat1 and read in a subsequent spi transac- tion. sample command: read digital filter registers 0x00 and 0x20. 02 03 00 00 02 00 00 00 [data] indicates data word returned from digital filter. (data) indicates multiple words of this type are to be written. name cmd 24-bit dat1 24-bit dat2 24-bit description nop 000000 - - no operation write df register 000001 reg data write digital filter register read df register 000002 reg [data] - - read digital filter register write fir coefficients 000003 num fir1 (fir coef) num fir2 (fir coef) write custom fir coefficients write iir coefficients 000004 a11 b11 a22 b21 b10 a21 b20 b22 write custom iir coefficients write rom coefficients 000005 coef sel - use on-chip coefficients write tbs data 000006 num tbs (tbs data) - (tbs data) write custom test bit stream data write rom tbs 000007 - - use on-chip tbs data filter start 000008 - - start digital filter operation filter stop 000009 - - stop digital filter operation table 7. microcontroller boot configuration commands
cs5376a 36 delay 1 ms, monitor sint , or poll e2dreq mosi: 03 06 00 00 00 miso: xx xx 07 04 31 02 03 00 00 02 00 00 20 delay 1 ms, monitor sint , or poll e2dreq mosi: 03 06 00 00 00 miso: xx xx 00 02 40 write fir coefficients - 0x03 this command writes custom coefficients for the fir1 and fir2 filters. the first two data words set the number of fir1 and fir2 coefficients to be written. the remaining data words are the concate- nated fir1 and fir2 coefficients. a maximum of 255 coefficients can be written for each fir filter, though the available digital filter computation cycles will limit their practical size. see ?fir filter? on page 47 for more information about fir filter coefficients. sample command: write fir1 coefficients 0x00022e, 0x000771 then fir2 coefficients 0xffffb9, 0xfffe8d. 02 03 00 00 03 00 00 02 00 00 02 delay 1 ms, monitor sint , or poll e2dreq 02 06 00 02 2e 00 07 71 delay 1 ms, monitor sint , or poll e2dreq 02 06 ff ff b9 ff fe 8d delay 1 ms, monitor sint , or poll e2dreq write iir coefficients - 0x04 this command writes custom coefficients for the two stage iir filter. the iir architecture and num- ber of coefficients is fixed, so eight coefficient val- ues immediately follow this command. the iir coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. see ?iir filter? on page 55 for more information about iir filter coefficients. sample command: write iir1 coefficients 0x84bc9d, 0x7da1b1, 0x825e4f, and iir2 coefficients 0x83694f, 0x3cad5f, 0x3e5104, 0x835df8, 0x3e5104. 02 03 00 00 04 84 bc 9d 7d a1 b1 delay 1 ms, monitor sint , or poll e2dreq 02 06 82 5e 4f 83 69 4f delay 1 ms, monitor sint , or poll e2dreq 02 06 3c ad 5f 3e 51 04 delay 1 ms, monitor sint , or poll e2dreq 02 06 83 5d f8 3e 51 04 delay 1 ms, monitor sint , or poll e2dreq write rom coefficients - 0x05 this configuration command selects the on-chip coefficients for fir1, fir2, iir 1st order, and iir 2nd order filters for use by the digital filter. one data word is required to select which internal coef- ficient sets to use. see ?filter coefficient selec- tion? on page 41 for information about selecting on-chip fir and iir coefficient sets. sample command: select iir1 and iir2 3 hz @ 500 sps low-cut co- efficients, with fir1 and fir2 linear phase high- cut coefficients. data word 0x002200. 02 03 00 00 05 00 22 00 delay 1 ms, monitor sint , or poll e2dreq write tbs data - 0x06 this command writes a custom data set for the test bit stream (tbs) generator. this command, along with the ability to program the test bit stream gen- erator interpolation and clock rate, can create cus- tom frequency test signals. the first data word sets the number of tbs data to be written and the remaining data words are the tbs data values. see ?test bit stream generator?
cs5376a 37 on page 64 for information about using custom test bit stream data sets. sample command: write test bit stream data 0x000000, 0x0007da, 0x000fb5, 0x00178f. 02 03 00 00 06 00 00 04 delay 1 ms, monitor sint , or poll e2dreq 02 06 00 00 00 00 07 da delay 1 ms, monitor sint , or poll e2dreq 02 06 00 0f b5 00 17 8f delay 1 ms, monitor sint , or poll e2dreq write tbs rom data - 0x07 this command selects the on-chip test bit stream (tbs) data for use by the tbs generator. no data words are required for this configuration com- mand. see ?test bit stream generator? on page 64 for information about the on-chip test bit stream data set. sample command: 02 03 00 00 07 delay 1 ms, monitor sint , or poll e2dreq filter start - 0x08 this command initializes and starts the digital fil- ter. measurement data becomes available one full sample period after this command is issued. no data words are required for this configuration com- mand. sample command: 02 03 00 00 08 delay 1 ms, monitor sint , or poll e2dreq filter stop - 0x09 this command disables the digital filter. measure- ment data output stops immediately after this com- mand is issued. no data words are required for this configuration command. sample command: 02 03 00 00 09 delay 1 ms, monitor sint , or poll e2dreq 9.5 example microcontroller configuration table 6 shows example microcontroller transac- tions for a minimal cs5376a configuration.
cs5376a 38 table 8. example microcontroller configuration transaction spi data description 01 02 03 00 00 05 00 22 00 write rom coefficients 02 delay 1ms, monitor sint , or poll e2dreq 03 02 03 00 00 07 write rom tbs data 04 delay 1ms, monitor sint , or poll e2dreq 05 02 03 00 00 01 00 00 00 07 04 31 write config register 06 delay 1ms, monitor sint , or poll e2dreq 07 02 03 00 00 01 00 00 20 00 02 40 write filtcfg register 08 delay 1ms, monitor sint , or poll e2dreq 09 02 03 00 00 01 00 00 2a 07 40 40 write tbscfg register 10 delay 1ms, monitor sint , or poll e2dreq 11 02 03 00 00 01 00 00 2b 04 b0 00 write tbsgain register 12 delay 1ms, monitor sint , or poll e2dreq 13 02 03 00 00 08 filter start
cs5376a 39 10. modulator interface the cs5376a performs digital filtering for up to four ? modulators. signals from the modulators are connected through the modulator data interface (mdi). 10.1 pin descriptions mclk, mclk/2 - pins 13, 12 modulator clock outputs. nominally 2.048 mhz and 1.024 mhz. msync - pin 14 modulator synchronization signal output. generat- ed from the sync input. mdata1 - mdata4 - pins 15, 17, 19, 21 modulator data inputs, nominally 512 kbit/s. mflag1 - mflag4 - pins 16, 18, 20, 22 modulator flag inputs. driven high when modula- tor is unstable due to an analog over-range signal. 10.2 modulator clock generation the mclk and mclk/2 outputs are low-jitter, low-skew modulator clocks generated from the 32.768 mhz master clock. mclk typically operates at 2.048 mhz unless an- alog low-power modes require a 1.024 mhz mod- ulator clock. mclk/2 always produces a clock at half the selected mclk rate. the mclk rate is selected and the mclk and mclk/2 outputs are enabled by bits in the digital filter config register (0x00). by default mclk and mclk/2 are disabled and driven low. 10.3 modulator synchronization the msync output signal follows an input on the sync pin. msync phase aligns the modulator sampling instant to guarantee synchronous analog sampling across a measurement network. msync is enabled by a bit in the config register (0x00). by default sync inputs do not cause an msync output. figure 20. modulator data interface fir iir filters filter output to high speed serial data port (sd port) dc offset correction output rate 4000 sps ~ 1 sps & gain mdata[4:1] mflag[4:1] mdi input 512 khz mclk / generate msync clk sync msync sinc filter mclk mclk/2
cs5376a 40 10.4 modulator data inputs the mdata input expects 1-bit ? data at a 512 khz or 256 khz rate. the input rate is selected by a bit in the config register (0x00). by default, mdata is expected at 512 khz. the mdata input one?s density is designed for full scale positive at 86% and full scale negative at 14%, with absolute maximum over-range capabili- ty to 93% and 7%. these raw ? inputs are deci- mated and filtered by the digital filter to create 24- bit samples at the output rate. 10.5 modulator flag inputs a high mflag input signal indicates the corre- sponding ? modulator has become unstable due to an analog over-range input signal. once the over-range signal is reduced, the modulator recov- ers stability and the mflag signal is cleared. the mflag inputs are mapped to status bits in the sd port, and are associated with each sample when written. see ?serial data port? on page 61 for more information on the mflag error bits in the sd port status byte.
cs5376a 41 11. digital filter initialization the cs5376a digital filter consists of three multi- stage sections: a three stage sinc filter, a two stage fir filter, and a two stage iir filter. to initialize the digital filter, fir and iir coeffi- cient sets are selected using configuration com- mands, and the filtcfg register (0x20) is written to select the output filter stage, the output word rate, and the number of enabled channels. the dig- ital filter clock rate is selected by writing the con- fig register (0x00). 11.1 filter coefficient selection selection of sinc filter coefficients is not required as they are selected automatically based on the pro- grammed output word rate. digital filter fir and iir coefficients are selected using the ?write fir coefficients? and ?write iir coefficients?, or the ?write rom coefficients? configuration commands. when writing the fir and iir coefficients from rom, a data word selects an on-chip coefficient set for each filter stage. fig- ure 22 shows the format of the coefficient selection word, and the available coefficient sets for each se- lection. characteristics of the on-chip digital filter coeffi- cients are discussed in the ?sinc filter?, ?fir fil- ter?, and ?iir filter? sections of this data sheet. 11.2 filter configuration options digital filter parameters are selected by bits in the filtcfg register (0x20), and the digital filter clock rate is selected by bits in the config regis- ter (0x00). 11.2.1 output filter stage the digital filter can output data following any stage in the filter chain. the output filter stage is se- lected by the fsel bits in the filtcfg register. taking data from the sinc or fir1 filter stages re- duces the overall decimation of the filter chain and increases the output rate, as discussed in the fol- lowing section. taking data from fir2, iir1, iir2, or iir3 results in data at the selected rate. figure 21. digital filter stages sinc filter 2 - 64000 fir1 4 fir2 2 iir1 iir2 1st order 2nd order output to high speed serial data port (sd port) dc offset correction output rate 4000 sps ~ 1 sps & gain modulator 512 khz input
cs5376a 42 11.2.2 output word rate the cs5376a digital filter supports output word rates (owrs) between 4000 sps and 1 sps. the output word rate is selected by the dec bits in the filtcfg register. when taking data directly from the sinc filter, the decimation of the fir1 and fir2 stages is by- passed and the actual output word rate is multiplied by a factor of eight compared with the register se- lection. when taking data directly from fir1, the decimation of the fir2 stage is bypassed and the actual output word rate is multiplied by a factor of two. data taken from the fir2, iir1, iir2, or iir3 filtering stages is output at the selected rate. 11.2.3 channel enable digital filtering can be performed simultaneously for up to four ? modulators. the number of en- abled channels is selected by the ch bits in the filtcfg register. channels are enabled sequentially. selecting one channel operation enables channel 1 only, selecting two channel operation enable s channels 1 and 2, se- lecting three channel opera tion enables channels 1, 2, and 3, and selecting four channel operation en- ables all four channels. 11.2.4 digital filter clock the digital filter clock rate is programmable be- tween 16.384 mhz and 32 khz by bits in the con- fig register. computation cycles the minimum digital filter clock rate for a config- uration depends on the computation cycles required to complete digital filter convolutions at the select- ed output word rate. all configurations work for a maximum digital filter clock, but lower clock rates consume less power. standby mode the cs5376a can be placed in a low-power stand- by mode by sending the ?filter stop? configuration command and programming the digital filter clock to 32 khz. in this mode the digital filter idles, con- suming minimal power until re-enabled by later configuration commands. bits 23:20 19:16 15:12 11:8 7:4 3:0 selection 0000 0000 iir2 iir1 fir2 fir1 figure 22. fir and iir coefficient set selection word bits 15:12 iir2 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 11:8 iir1 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 7:4 fir2 coefficients 0000 linear phase 0001 minimum phase bits 3:0 fir1 coefficients 0000 linear phase 0001 minimum phase
cs5376a 43 12. sinc filter the sinc filters primary purpose is to attenuate out-of-band noise components from the ? modu- lators. while doing so, they decimate 1-bit ? data into lower frequency 24-bit data suitable for the fir and iir filters. the sinc filter has three cascaded sections, sinc1, sinc2, and sinc3, which are each made up of the smaller stages shown in figure 23. the selected output word rate in the filtcfg reg- ister automatically determines the coefficients and decimation ratios selected for the sinc filters. once the sinc filter configuration is set, all en- abled channels are filtered and decimated using an identical hardware algorithm. 12.1 sinc1 filter the first section is sinc1, a single stage 5th order fixed decimate by 8 sinc filter. this sinc filter decimates the incoming 1-bit ? bit stream from the modulators down to a 64 khz rate. 12.2 sinc2 filter the second section is sinc2, a multi-stage, vari- able order, variable decimation sinc filter. de- pending on the selected output word rate in the filtcfg register, different cascaded sinc2 stag- es are enabled, as shown in table 9. 12.3 sinc3 filter the last section is sinc3, a flexible multi-stage variable order, variable decimation sinc filter. depending on the selected output word rate in the filtcfg register, different sinc3 stages are en- abled, as shown in table 9. 12.4 sinc filter synchronization the sinc filter is synchronized to the external sys- tem by the msync signal, which is generated from the sync input. the msync signal sets a reference time (time 0) for all filter operations, and the sinc filter is restarted to phase align with this reference time. sinc1 8 5th order 4th order figure 23. sinc filter block diagram 1-bit 24-bit ?? 2 stage1 sinc2 4th order 2 stage2 sinc2 4th order 2 stage3 sinc2 4th order 2 stage4 sinc2 4th order 5 stage1 sinc3 4th order 5 stage2 sinc3 4th order 5 stage3 sinc3 5th order 2 stage4 sinc3 6th order 2 stage5 sinc3 6th order 3 stage6 sinc3 output input
cs5376a 44 sinc1 ? single stage, fixed decimate by 8 5 th order decimate by 8, 36 coefficients sinc2 ? multi-stage, variable decimation stage 1: 4 th order decimate by 2, 5 coefficients stage 2: 4 th order decimate by 2, 5 coefficients stage 3: 5 th order decimate by 2, 6 coefficients stage 4: 6 th order decimate by 2, 7 coefficients sinc3 ? multi-stage, variable decimation stage 1: 4 th order decimate by 5, 17 coefficients stage 2: 4 th order decimate by 5, 17 coefficients stage 3: 4 th order decimate by 5, 17 coefficients stage 4: 5 th order decimate by 2, 6 coefficients stage 5: 6 th order decimate by 2, 7 coefficients stage 6: 6 th order decimate by 3, 13 coefficients figure 24. sinc filter stages sinc filters fir2 output word rate dec bit setting sinc1 deci- mation sinc2 deci- mation sinc2 stages sinc3 deci- mation sinc3 stages 4000 0111 8 2 4 - - 2000 0110 8 4 3,4 - - 1000 0101 8 8 2,3,4 - - 500 0100 8 16 1,2,3,4 - - 333 0011 8 8 2,3,4 3 6 250 0010 8 16 1,2,3,4 2 5 200 0001 8 2 4 20 3,4,5 125 0000 8 16 1,2,3,4 4 4,5 100 1111 8 4 3,4 20 3,4,5 50 1110 8 8 2,3,4 20 3,4,5 40 1101 8 2 4 100 2,3,4,5 25 1100 8 16 1,2,3,4 20 3,4,5 20 1011 8 4 3,4 100 2,3,4,5 10 1010 8 8 2,3,4 100 2,3,4,5 5 1001 8 16 1,2,3,4 100 2,3,4,5 1 1000 8 16 1,2,3,4 500 1,2,3,4,5 table 9. sinc filter configurations
cs5376a 45 filter type system function filter coefficients sinc2 (stage 1) sinc2 (stage 2) 4 th order decimate by 2 5 coefficients 4 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 4 h 2 = 6 h 3 = 4 h 4 = 1 sinc2 (stage 3) 5 th order decimate by 2 6 coefficients 5 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 5 h 2 = 10 h 3 = 10 h 4 = 5 h 5 = 1 sinc2 (stage 4) 6 th order decimate by 2 7 coefficients 6 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 6 h 2 = 15 h 3 = 20 h 4 = 15 h 5 = 6 h 6 = 1 filter type system function filter coefficients sinc1 5 th order decimate by 8 36 coefficients 5 1 8 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 18 = 2460 h 1 = 5 h 19 = 2380 h 2 = 15 h 20 = 2226 h 3 = 35 h 21 = 2010 h 4 = 70 h 22 = 1750 h 5 = 126 h 23 = 1470 h 6 = 210 h 24 = 1190 h 7 = 330 h 25 = 926 h 8 = 490 h 26 = 690 h 9 = 690 h 27 = 490 h 10 = 926 h 28 = 330 h 11 = 1190 h 29 = 210 h 12 = 1470 h 30 = 126 h 13 = 1750 h 31 = 70 h 14 = 2010 h 32 = 35 h 15 = 2226 h 33 = 15 h 16 = 2380 h 34 = 5 h 17 = 2460 h 35 = 1 table 10. sinc1 and sinc2 filter coefficients
cs5376a 46 filter type system function filter coefficients sinc3 (stage 1) sinc3 (stage 2) sinc3 (stage 3) 4 th order decimate by 5 17 coefficients 4 1 5 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 4 h 2 = 10 h 3 = 20 h 4 = 35 h 5 = 52 h 6 = 68 h 7 = 80 h 8 = 85 h 9 = 80 h 10 = 68 h 11 = 52 h 12 = 35 h 13 = 20 h 14 = 10 h 15 = 4 h 16 = 1 sinc3 (stage 4) 5 th order decimate by 2 6 coefficients 5 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 5 h 2 = 10 h 3 = 10 h 4 = 5 h 5 = 1 sinc3 (stage 5) 6 th order decimate by 2 7 coefficients 6 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 6 h 2 = 15 h 3 = 20 h 4 = 15 h 5 = 6 h 6 = 1 sinc3 (stage 6) 6 th order decimate by 3 13 coefficients 6 1 3 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 6 h 2 = 21 h 3 = 50 h 4 = 90 h 5 = 126 h 6 = 141 h 7 = 126 h 8 = 90 h 9 = 50 h 10 = 21 h 11 = 6 h 12 = 1 table 11. sinc3 filter coefficients
cs5376a 47 13. fir filter the finite impulse response (fir) filter block con- sists of two cascaded stages, fir1 and fir2. it compensates for sinc filter droop and creates a low-pass corner to block aliased components of the input signal. on-chip linear phase or minimum phase coeffi- cients can be selected using a configuration com- mand, or the coefficients can be programmed for a custom filter response. 13.1 fir1 filter the fir1 filter stage has a decimate by four archi- tecture. it compensates for sinc filter droop and flattens the magnitude response of the pass band. the on-chip linear and minimum phase coefficient sets are 48-tap, with a maximum 255 programma- ble coefficients. all coefficients are normalized to 24-bit two?s complement full scale, 0x7fffff. the characteristic equation for fir1 is a convolu- tion of the input values, x(n), and the filter coeffi- cients, h(k), to produce an output value, y. y = [h(k)*x(n-k)] + [h(k+1)*x(n-(k+1))] + ... 13.2 fir2 filter the fir2 filter stage has a decimate by two archi- tecture. it creates a low-pass brick wall filter to block aliased components of the input signal. the on-chip linear and minimum phase coefficient sets are 126-tap, with a maximum 255 programma- ble coefficients. all coefficients are normalized to 24-bit two?s complement full scale, 0x7fffff. the characteristic equation for fir2 is a convolu- tion of the input values, x(n), and the filter coeffi- cients, h(k), to produce an output value, y. y = [h(k)*x(n-k)] + [h(k+1)*x(n-(k+1))] + ... 13.3 on-chip fir coefficients two sets of on-chip linear phase and minimum phase coefficients are available for fir1 and fir2. performance of the on-chip coefficient sets is very good, with excellent ripple and stop band charac- teristics as described in figure 26 and table 12. which on-chip coefficient set to use is selected by a data word following the ?write rom coeffi- cients? configuration command. see ?filter coeffi- cient selection? on page 41 for information about selecting on-chip coefficient sets. fir1 filter - decimate by 4 fir2 filter - decimate by 2 figure 25. fir filter block diagram
cs5376a 48 13.4 programmable fir coefficients a maximum of 255 + 255 coefficients can be pro- grammed into fir1 and fir2 to create a custom filter response. the total number of coefficients for the fir filter is fundamentally limited by the avail- able computation cycles in the digital filter, which itself is determined by the digital filter clock rate. custom filter sets should normalize the maximum coefficient value to 24-bit two?s complement full scale, 0x7fffff, and scale all other coefficients accordingly. to maintain maximum internal dy- namic range, the cs5376a fir filter performs double precision calculations with an automatic gain correction to scale the final output. custom fir coefficients are uploaded using the ?write fir coefficients? configuration command. see ?eeprom configuration commands? on page 28 or ?microcontroller configuration com- mands? on page 35 for information about writing custom fir coefficients. 13.5 fir filter synchronization the fir1 and fir2 filters are synchronized to the external system by the msync signal, which is generated from the sync input. the msync sig- nal sets a reference time (time 0) for all filter oper- ations, and the fir filters are restarted to phase align with this reference time.
cs5376a 49 fir1 ? single stage, fixed decimate by 4 coefficient set 0: linear phase decimate by 4, 48 coefficients coefficient set 1: minimum phase decimate by 4, 48 coefficients sinc droop compensation filter fir2 ? single stage, fixed decimate by 2 coefficient set 0: linear phase decimate by 2, 126 coefficients coefficient set 1: minimum phase decimate by 2, 126 coefficients brick wall low-pass filter, flat to 40% f s combined sinc + fir digital filter specifications passband ripple less than +/- 0.01 db below 40% f s transition band -3 db frequency at 42.89% f s stopband attenuation greater than 130 db above 50% f s figure 26. fir filter stages sinc + fir filters fir2 output word rate sinc deci- mation fir1 deci- mation fir2 deci- mation total deci- mation passband ripple ( db) stopband atten- uation (db) 4000 16 4 2 128 0.0042 130.38 2000 32 4 2 256 0.0045 130.38 1000 64 4 2 512 0.0040 130.42 500 128 4 2 1024 0.0041 130.42 333 192 4 2 1536 0.0080 130.45 250 256 4 2 2048 0.0064 130.43 200 320 4 2 2560 0.0041 130.43 125 512 4 2 4096 0.0046 130.42 100 640 4 2 5120 0.0040 130.43 50 1280 4 2 10240 0.0040 130.43 40 1600 4 2 12800 0.0036 130.43 25 2560 4 2 20480 0.0040 132.98 20 3200 4 2 25600 0.0036 130.43 10 6400 4 2 51200 0.0036 130.43 5 12800 4 2 102400 0.0036 130.43 1 64000 4 2 512000 0.0029 134.31 table 12. fir filter characteristics
cs5376a 50 individual filter stage group delay (no iir) decimation ratios number of coefficients group delay (filter stage input rate) sinc1 8 36 17.5 sinc2 stage 4 2 7 3.0 stages 3,4 2,2 6,7 8.5 stages 2,3,4 2,2,2 5,6,7 19.0 stages 1,2,3,4 2,2,2,2 5,5,6,7 40.0 sinc3 stage 6 3 13 6.0 stage 5 2 7 3.0 stages 4,5 2,2 6,7 8.5 stages 3,4,5 5,2,2 17,6,7 50.5 stages 2,3,4,5 5,5,2,2 17,17,6,7 260.5 stages 1,2,3,4,5 5,5,5,2,2 17,17,17,6,7 1310.5 fir1 coefficient set 0 4 48 23.5 coefficient set 1 4 48 see figure fir2 coefficient set 0 2 126 62.5 coefficient set 1 2 126 see figure cumulative linear phase group delay (no iir) fir2 output word rate sinc output group delay (sinc filter input rate) fir1 output group delay (sinc filter input rate) fir2 output group delay (sinc filter input rate) fir2 output group delay (fir2 output word rate) 4000 41.5 417.5 4417.5 34.5117 2000 85.5 837.5 8837.5 34.5215 1000 169.5 1673.5 17673.5 34.5186 500 337.5 3345.5 35345.5 34.5171 333 553.5 5065.5 53065.5 34.5479 250 721.5 6737.5 70737.5 34.5398 200 849.5 8369.5 88369.5 34.5193 125 1425.5 13457.5 141457.5 34.5355 100 1701.5 16741.5 176741.5 34.5198 50 3401.5 33481.5 353481.5 34.5197 40 4209.5 41809.5 441809.5 34.5164 25 6801.5 66961.5 706961.5 34.5196 20 8421.5 83621.5 883621.5 34.5165 10 16841.5 167241.5 1767241.5 34.5164 5 33681.5 334481.5 3534481.5 34.5164 1 168081.5 1672081.5 17672081.5 34.5158 table 13. sinc + fir group delay
cs5376a 51 minimum phase group delay fir1 minimum phase group delay (normalized frequency) fir2 minimum phase group delay (normalized frequency) table 14. minimum phase group delay
cs5376a 52 filter type filter coefficients (normalized 24-bit) fir1 (coefficient set 0) low pass, sinc compensation linear phase decimate by 4 48 coefficients h 0 = 558 h 24 = 8388607 h 1 = 1905 h 25 = 7042723 h 2 = 3834 h 26 = 4768946 h 3 = 5118 h 27 = 2266428 h 4 = 365 h 28 = 189436 h 5 = -14518 h 29 = -1053303 h 6 = -39787 h 30 = -1392827 h 7 = -67365 h 31 = -1084130 h 8 = -69909 h 32 = -496361 h 9 = -19450 h 33 = 39864 h 10 = 97434 h 34 = 332367 h 11 = 258881 h 35 = 375562 h 12 = 375562 h 36 = 258881 h 13 = 332367 h 37 = 97434 h 14 = 39864 h 38 = -19450 h 15 = -496361 h 39 = -69909 h 16 = -1084130 h 40 = -67365 h 17 = -1392827 h 41 = -39787 h 18 = -1053303 h 42 = -14518 h 19 = 189436 h 43 = 365 h 20 = 2266428 h 44 = 5118 h 21 = 4768946 h 45 = 3834 h 22 = 7042723 h 46 = 1905 h 23 = 8388607 h 47 = 558 fir1 (coefficient set 1) low pass, sinc compensation minimum phase decimate by 4 48 coefficients h 0 = 3337 h 24 = 555919 h 1 = 22258 h 25 = -165441 h 2 = 88284 h 26 = -581479 h 3 = 266742 h 27 = -617500 h 4 = 655747 h 28 = -388985 h 5 = 1371455 h 29 = -99112 h 6 = 2502684 h 30 = 114761 h 7 = 4031988 h 31 = 186557 h 8 = 5783129 h 32 = 141374 h 9 = 7396359 h 33 = 58582 h 10 = 8388607 h 34 = -12664 h 11 = 8325707 h 35 = -42821 h 12 = 6988887 h 36 = -35055 h 13 = 4531706 h 37 = -16792 h 14 = 1507479 h 38 = 367 h 15 = -1319126 h 39 = 7929 h 16 = -3207750 h 40 = 5926 h 17 = -3736028 h 41 = 2892 h 18 = -2980701 h 42 = 23 h 19 = -1421498 h 43 = -1164 h 20 = 237307 h 44 = -538 h 21 = 1373654 h 45 = -238 h 22 = 1711919 h 46 = 18 h 23 = 1322371 h 47 = 113 figure 27. fir1 coefficients
cs5376a 53 filter type filter coefficients (normalized 24-bit) fir2 (coefficient set 0) low pass, passband to 40% f s linear phase decimate by 2 126 coefficients h 0 = -71 h 63 = 8388607 h 1 = -371 h 64 = 3875315 h 2 = -870 h 65 = -766230 h 3 = -986 h 66 = -1854336 h 4 = 34 h 67 = -137179 h 5 = 1786 h 68 = 1113788 h 6 = 2291 h 69 = 454990 h 7 = 291 h 70 = -642475 h 8 = -2036 h 71 = -553873 h 9 = -943 h 72 = 298975 h 10 = 2985 h 73 = 533334 h 11 = 3784 h 74 = -49958 h 12 = -1458 h 75 = -443272 h 13 = -5808 h 76 = -116005 h 14 = -1007 h 77 = 318763 h 15 = 7756 h 78 = 208018 h 16 = 5935 h 79 = -187141 h 17 = -7135 h 80 = -238025 h 18 = -11691 h 81 = 68863 h 19 = 3531 h 82 = 221211 h 20 = 17500 h 83 = 22850 h 21 = 4388 h 84 = -174452 h 22 = -20661 h 85 = -81993 h 23 = -15960 h 86 = 114154 h 24 = 18930 h 87 = 109009 h 25 = 29808 h 88 = -54172 h 26 = -9795 h 89 = -109189 h 27 = -42573 h 90 = 4436 h 28 = -7745 h 91 = 90744 h 29 = 49994 h 92 = 29702 h 30 = 33021 h 93 = -62651 h 31 = -47092 h 94 = -47092 h 32 = -62651 h 95 = 33021 h 33 = 29702 h 96 = 49994 h 34 = 90744 h 97 = -7745 h 35 = 4436 h 98 = -42573 h 36 = -109189 h 99 = -9795 h 37 = -54172 h 100 = 29808 h 38 = 109009 h 101 = 18930 h 39 = 114154 h 102 = -15960 h 40 = -81993 h 103 = -20661 h 41 = -174452 h 104 = 4388 h 42 = 22850 h 105 = 17500 h 43 = 221211 h 106 = 3531 h 44 = 68863 h 107 = -11691 h 45 = -238025 h 108 = -7135 h 46 = -187141 h 109 = 5935 h 47 = 208018 h 110 = 7756 h 48 = 318763 h 111 = -1007 h 49 = -116005 h 112 = -5808 h 50 = -443272 h 113 = -1458 h 51 = -49958 h 114 = 3784 h 52 = 533334 h 115 = 2985 h 53 = 298975 h 116 = -943 h 54 = -553873 h 117 = -2036 h 55 = -642475 h 118 = 291 h 56 = 454990 h 119 = 2291 h 57 = 1113788 h 120 = 1786 h 58 = -137179 h 121 = 34 h 59 = -1854336 h 122 = -986 h 60 = -766230 h 123 = -870 h 61 = 3875315 h 124 = -371 h 62 = 8388607 h 125 = -71 figure 28. fir2 linear phase coefficients
cs5376a 54 filter type filter coefficients (normalized 24-bit) fir2 (coefficient set 1) low pass, passband to 40% f s minimum phase decimate by 2 126 coefficients h 0 = 4019 h 63 = 67863 h 1 = 43275 h 64 = -190800 h 2 = 235427 h 65 = -128546 h 3 = 848528 h 66 = 114197 h 4 = 2240207 h 67 = 147750 h 5 = 4525758 h 68 = -46352 h 6 = 7077833 h 69 = -143269 h 7 = 8388607 h 70 = -13290 h 8 = 6885673 h 71 = 114721 h 9 = 2483461 h 72 = 51933 h 10 = -2538963 h 73 = -75952 h 11 = -4800543 h 74 = -68746 h 12 = -2761696 h 75 = 38171 h 13 = 1426109 h 76 = 68492 h 14 = 3624338 h 77 = -7856 h 15 = 1820814 h 78 = -57526 h 16 = -1695825 h 79 = -12540 h 17 = -2885148 h 80 = 41717 h 18 = -605252 h 81 = 23334 h 19 = 2135021 h 82 = -25516 h 20 = 1974197 h 83 = -26409 h 21 = -630111 h 84 = 11717 h 22 = -2168177 h 85 = 24246 h 23 = -750147 h 86 = -1620 h 24 = 1516192 h 87 = -19248 h 25 = 1550127 h 88 = -4610 h 26 = -508445 h 89 = 13356 h 27 = -1686937 h 90 = 7526 h 28 = -437822 h 91 = -7887 h 29 = 1308705 h 92 = -8016 h 30 = 1069556 h 93 = 3559 h 31 = -657282 h 94 = 7023 h 32 = -1301014 h 95 = -598 h 33 = -30654 h 96 = -5350 h 34 = 1173754 h 97 = -1097 h 35 = 579643 h 98 = 3579 h 36 = -803111 h 99 = 1806 h 37 = -895851 h 100 = -2058 h 38 = 328399 h 101 = -1859 h 39 = 962522 h 102 = 936 h 40 = 124678 h 103 = 1558 h 41 = -820948 h 104 = -224 h 42 = -466657 h 105 = -1129 h 43 = 545674 h 106 = -152 h 44 = 652827 h 107 = 718 h 45 = -220448 h 108 = 290 h 46 = -680495 h 109 = -395 h 47 = -80886 h 110 = -290 h 48 = 578844 h 111 = 178 h 49 = 306445 h 112 = 227 h 50 = -395302 h 113 = -53 h 51 = -431004 h 114 = -151 h 52 = 181900 h 115 = -5 h 53 = 454403 h 116 = 86 h 54 = 15856 h 117 = 23 h 55 = -395525 h 118 = -42 h 56 = -166123 h 119 = -22 h 57 = 284099 h 120 = 17 h 58 = 253485 h 121 = 14 h 59 = -152407 h 122 = -5 h 60 = -277888 h 123 = -7 h 61 = 28526 h 124 = 1 h 62 = 250843 h 125 = 3 figure 29. fir2 minimum phase coefficients
cs5376a 55 14. iir filter the infinite impulse response (iir) filter block consists of two cascaded stages, iir1 and iir2. it creates a high-pass corner to block very low-fre- quency and dc components of the input signal. on-chip iir1 and iir2 coefficients can be selected using a configuration command, or the coefficients can be programmed for a custom filter response. 14.1 iir architecture the architecture of the iir filter is automatically determined when the output filter stage is selected in the filtcfg register. selecting the 1st order iir1 filter bypasses the 2nd order stage, while se- lecting the 2nd order iir2 filter bypasses the 1st or- der stage. selection of the 3rd order iir3 filter enables both the 1st and 2nd order stages. 14.2 iir1 filter the 1st order iir filter stage is a direct form filter with three coefficients: a11, b10, and b11. coeffi- cients of a 1st order iir are inherently normalized to one, and should be scaled to 24-bit two?s com- plement full scale, 0x7fffff. the characteristic equations for the 1st order iir include an input value, x, an output value, y, and two intermediate values, w1 and w2, separated by a delay element (z -1 ). w2 = w1 w1 = x + (-a11 * w2) y = (w1 * b10) + (w2 * b11) 14.3 iir2 filter the 2nd order iir filter stage is a direct form filter with five coefficients: a21, a22, b20, b21, and b22. coefficients of a 2nd order iir are inherently nor- malized to two, and should be scaled to 24-bit two?s complement full scale, 0x7fffff. normal- ization effectively divides the 2nd order coeffi- cients in half relative to the input, and requires modification of the characteristic equations. the characteristic equations for the 2nd order iir include an input value, x, an output value, y, and three intermediate values, w3, w4, and w5, each separated by a delay element (z -1 ). the following z -1 z -1 z -1 -a 11 b 11 b 10 -a 21 -a 22 b 21 b 22 b 20 figure 30. iir filter block diagram 1st order iir1 2nd order iir2 3rd order iir3 implemented by running both iir1 and iir2 stages
cs5376a 56 characteristic equations model the operation of the 2nd order iir filter with unnormalized coefficients. w5 = w4 w4 = w3 w3 = x + (-a21 * w4) + (-a22 * w5) y = (w3 * b20) + (w4 * b21) + (w5 * b22) internally, the cs5376a uses normalized coeffi- cients to perform the 2nd order iir filter calcula- tion, which changes the algorithm slightly. the following characteristic equations model the oper- ation of the 2nd order iir filter when using normal- ized coefficients. w5 = w4 w4 = w3 w3 = 2 * [(x / 2) + (-a21 * w4) + (-a22 * w5)] y = 2 * [(w3 * b20) + (w4 * b21) + (w5 * b22)] 14.4 iir3 filter the 3rd order iir filter is implemented by running both the 1st order and 2nd order iir filter stages. it can be modeled by cascading the characteristic equations of the 1st order and 2nd order iir stages. 14.5 on-chip iir coefficients five sets of on-chip coefficients are available for iir1 and iir2, each providing a 3 hz high-pass butterworth response at different output word rates. characteristics of the on-chip coefficient sets are described in figure 31 and table 14. which on-chip coefficient set to use is selected by a data word following the ?write rom coeffi- cients? configuration command. see ?filter coeffi- cient selection? on page 41 for information about selecting on-chip coefficient sets. 14.6 programmable iir coefficients a maximum of 3 + 5 coefficients can be pro- grammed into iir1 and iir2 to create a custom fil- ter response. custom filter sets should normalize the coefficients to 24-bit two?s complement full scale, 0x7fffff. to maintain maximum internal dynamic range, the cs5376a iir filter performs double precision calculations with an automatic gain correction to scale the final output. custom iir coefficients are uploaded using the ?write iir coefficients? configuration command. see ?eeprom configuration commands? on page 28 or ?microcontroller configuration com- mands? on page 35 for information about writing custom iir coefficients. 14.7 iir filter synchronization the iir filter is not synchronized to the external system directly, only indirectly through the syn- chronization of the sinc and fir filters. because iir filters have ?infinite? memory, a discontinuity in the input data stream from a synchronization event can require significant time to settle out. the exact settling time depends on the size of the dis- continuity and the filter coefficient characteristics.
cs5376a 57 iir1 ? single stage, no decimation 1 st order no decimation, 3 coefficients coefficient set 0: high-pass, corner 0.15% f s (3 hz at 2000 sps) coefficient set 1: high-pass, corner 0.30% f s (3 hz at 1000 sps) coefficient set 2: high-pass, corner 0.60% f s (3 hz at 500 sps) coefficient set 3: high-pass, corner 0.90% f s (3 hz at 333 sps) coefficient set 4: high-pass, corner 1.20% f s (3 hz at 250 sps) iir2 ? single stage, no decimation 2 nd order no decimation, 5 coefficients coefficient set 0: high-pass, corner 0.15% f s (3 hz at 2000 sps) coefficient set 1: high-pass, corner 0.30% f s (3 hz at 1000 sps) coefficient set 2: high-pass, corner 0.60% f s (3 hz at 500 sps) coefficient set 3: high-pass, corner 0.90% f s (3 hz at 333 sps) coefficient set 4: high-pass, corner 1.20% f s (3 hz at 250 sps) iir3 ? two stage, no decimation 3 rd order no decimation, 8 coefficients (combined iir1 and iir2 filter responses) coefficient set 0,0: high-pass, corner 0.20% f s (4 hz at 2000 sps) coefficient set 1,1: high-pass, corner 0.41% f s (4 hz at 1000 sps) coefficient set 2,2: high-pass, corner 0.82% f s (4 hz at 500 sps) coefficient set 3,3: high-pass, corner 1.22% f s (4 hz at 333 sps) coefficient set 4,4: high-pass, corner 1.63% f s (4 hz at 250 sps) figure 31. iir filter stages iir filters iir1 coeff selection iir1 corner frequency iir2 coeff selection iir2 corner frequency iir3 coeff selection iir3 corner frequency 0 0.15% f s 0 0.15% f s 0,0 0.2041% f s 1 0.30% f s 1 0.30% f s 1,1 0.4074% f s 2 0.60% f s 2 0.60% f s 2,2 0.8152% f s 3 0.90% f s 3 0.90% f s 3,3 1.2222% f s 4 1.20% f s 4 1.20% f s 4,4 1.6293% f s table 14. iir filter characteristics
cs5376a 58 filter type system function filter coefficients (normalized 24-bit) iir1 (coefficient set 0) 1 st order, high pass corner at 0.15% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8309916 b 10 = 8349262 b 11 = -8349262 iir1 (coefficient set 1) 1 st order, high pass corner at 0.30% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8231957 b 10 = 8310282 b 11 = -8310282 iir1 (coefficient set 2) 1 st order, high pass corner at 0.60% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8078179 b 10 = 8233393 b 11 = -8233393 iir1 (coefficient set 3) 1 st order, high pass corner at 0.90% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -7927166 b 10 = 8157887 b 11 = -8157887 iir1 (coefficient set 4) 1 st order, high pass corner at 1.20% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -7778820 b 10 = 8083714 b 11 = -8083714 filter type system function filter coefficients (normalized 24-bit) iir2 (coefficient set 0) 2 nd order, high pass corner at 0.15% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8332704 a 22 = 4138771 b 20 = 4166445 b 21 = -8332890 b 22 = 4166445 iir2 (coefficient set 1) 2 nd order, high pass corner at 0.30% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8276806 a 22 = 4083972 b 20 = 4138770 b 21 = -8277540 b 22 = 4138770 iir2 (coefficient set 2) 2 nd order, high pass corner at 0.60% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8165041 a 22 = 3976543 b 20 = 4083972 b 21 = -8167944 b 22 = 4083972 iir2 (coefficient set 3) 2 nd order, high pass corner at 0.90% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8053350 a 22 = 3871939 b 20 = 4029898 b 21 = -8059796 b 22 = 4029898 iir2 (coefficient set 4) 2 nd order, high pass corner at 1.20% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -7941764 a 22 = 3770088 b 20 = 3976539 b 21 = -7953078 b 22 = 3976539 table 15. iir filter coefficients
cs5376a 59 15. gain and offset correction the cs5376a digital filter can apply independent gain and offset corrections to the data of each mea- surement channel. also, an offset calibration algo- rithm can automatically calculate offset correction values for each channel. gain correction values are written to the gainx registers (0x21-0x24), while offset correction val- ues are written to the offsetx registers (0x25- 0x28). gain and offset corrections are enabled by the usegr and useor bits in the filtcfg reg- ister (0x20). when enabled, the offset calibration algorithm will automatically calculate offset correction values for each channel and write them into the offsetx registers. offset calibration is enabled by writing the exp and orcal bits in filtcfg. 15.1 gain correction gain correction in the cs5376a normalizes sensor gains in multi-sensor networks. it requires exter- nally calculated correction values to be written into the gainx registers (0x21-0x24). gain correction values are 24-bit two?s comple- ment with unity gain defined as full scale, 0x7fffff. gain correction always scales to a frac- tional value, and can never gain the digital filter data greater than one. output value = data * (gain / 0x7fffff) unity gain: gain = 0x7fffff 50% gain: gain = 0x3fffff zero gain: gain = 0x000000 once the gain registers are written, the usegr bit in the filtcfg register enables gain correc- tion. 15.2 offset correction offset correction in the cs5376a cancels the dc bias of a measurement channel by subtracting the figure 32. gain and offset correction fir iir filters filter output to high speed serial data port (sd port) offset correction output rate 4000 sps ~ 1 sps sinc filter mdi input 512 khz correction gain offset calibration 4 4 4 4
cs5376a 60 value in the offsetx registers (0x25-0x28) from the digital filter output data word. offset correction values are 24-bit two?s comple- ment with a maximum positive value of 0x7fffff, and a maximum negative value of 0x800000. if ap- plying an offset correction causes the final result to exceed a 24-bit two?s complement maximum, the output data will saturate to that maximum value. output data = input data - offset correction max positive output value = 0x7fffff max negative output value = 0x800000 once the offset registers are written, the use- or bit in the filtcfg register enables offset cor- rection. 15.3 offset calibration an offset calibration algorithm in the cs5376a can automatically calculate offset correction val- ues. when using the offset calibration algorithm, background noise data should be used as the basis for calculating the offset value of each measure- ment channel. the offset calibration algorithm is an exponential averaging function that places increased weight on more recent digital filte r data. the exponential weighting factor is set by the exp bits in the filtcfg register, with larger exponent values producing a smoother averaging function that re- quires a longer settling time, and smaller values producing a noisier averaging function that re- quires a shorter settling time. typical exponential values range from 0x05 to 0x0f, depending on the available settling time. the characteristic equations of the offset calibra- tion algorithm include an input value, x, an output value, y, a summation value, ysum, a sample in- dex, n, and an exponential value, exp. y(n) = x(n) - [ysum(n-1) >> exp] ysum(n) = y(n) + ysum(n-1) offset correction = ysum >> exp once the exp bits are written, the orcal bit in the filtcfg register is set to enable offset calibra- tion. when enabled, updated offset correction val- ues are automatically written to the offsetx registers. when the offset calibration algorithm is fully settled, the orcal bit is cleared to maintain the final values in the offsetx registers.
cs5376a 61 16. serial data port once digital filtering is complete, each 24-bit out- put sample is combined with an 8-bit status byte. these 32-bit data words are written to an 8-deep fifo buffer and then transmitted to the communi- cations channel through a high speed serial data port (sd port). 16.1 pin descriptions sdtki - pin 64 token input, requests an sd port transaction. sdrdy - pin 61 data ready output signal, active low. open drain output requiring a 10 k ? pull-up resistor. sdclk - pin 62 serial clock input. sddat - pin 60 serial data output. data valid on rising edge of sdclk, transition on falling edge. sdtko - pin 63 token output, ends an sd port transaction. passes through the sdtki signal when no data is available in the sd port output fifo. 16.2 sd port data format serial data transactions transfer 32-bit words. each word consists of an 8-bit status byte followed by a 24-bit output sample. the status byte, shown in figure 34, has an mflag bit, channel bits, a time break bit, and a fifo overflow bit. mflag bit - mflag the mflag bit is set when an mflag signal is received on the mflag1-mflag4 pins. when received, that channel mflag bit is set in the next output word. see ?modulator interface? on page 39 for more information about mflag. channel bits - ch[1:0] channel bits indicate from which conversion chan- nel the data word is from. the channel number, ch[1:0], is zero based. ch[1:0] = 00 = channel 1 ch[1:0] = 01 = channel 2 ch[1:0] = 10 = channel 3 ch[1:0] = 11 = channel 4 time break bit - tb the time break bit marks a timing reference based on a rising edge into the timeb pin. after a pro- grammed delay, the tb bit in the status byte is set cs5376a sdtki sdtko figure 33. serial data port block diagram system telemetry sddat sdrdy sdclk token out token in data ready data in clock out
cs5376a 62 for one output sample in all channels. the time- brk digital filter register (0x29) programs the sample delay for the tb bit output. see ?time break controller? on page 68 for more information about time break. fifo overflow bit - w the fifo overflow bit indicates an error condition in the sd port data fifo, and is set if new digital filter data overwrites a fifo location containing data which has not yet been sent. the w bit is sticky, meaning it persists indefinitely once set. clearing the w bit requires sending the ?filter stop? and ?filter start? configuration com- mands to reinitialize the data fifo. conversion data word the lower 24-bits of the sd port output data word is the conversion sample for the specified channel. conversion data is 24-bit two?s complement for- mat. 16.3 sd port transactions the sd port can operate in two modes depending how the sdtki pin is connected: request mode where data is output when requested by the com- munications channel, or continuous mode where data is output immediately when ready. 16.3.1 request mode to initiate sd port transactions on request, sdtki is connected to an active high polling signal from the communications channel. a rising edge into sdtki when new data is available in the sd port fifo causes the cs5376a to initiate an sd port transaction by driving sdrdy low. if data is not yet available in the sd port fifo, the sdtki sig- nal is passed through to the sdtko output. once an sd port transaction is initiated, serial clocks into sdclk cause data to be output to sddat, as shown in figure 35. when all available data status 0 23 31 -- mflag ch[1] ch[0] w 31 29 30 28 27 26 25 24 figure 34. sd port data format tb -- word 1 word 4 word 2 word 3 status data 128 bits -- 00 - channel 1 01 - channel 2 10 - channel 3 11 - channel 4 0 - modulator ok 1 - modulator error 0 - no time break 1 - time break 0 - fifo ok 1 - fifo overflow
cs5376a 63 data is read from the sd port data fifo, sdrdy is released and sdtko is pulsed high for 100 ns. 16.3.2 continuous mode to have the cs5376a au tomatically initiate sd port transactions whenever data becomes available, connect sdtki to a 4 mhz or slower clock source such as mclk/2. the first rising edge into sdtki after data becomes available in the sd port fifo causes the cs5376a to initiate an sd port transac- tion by driving sdrdy low. if data is not available in the sd port fifo, the sdtki signal is passed through to the sdtko output. once an sd port transaction is initiated, serial clocks into sdclk cause data to be output to sddat, as shown in figure 35. when all available data is read from the sd port data fifo, sdrdy is released and sdtko is pulsed high for 100 ns. sdrdy sdclk sddat figure 35. sd port transaction msb lsb sdtki sdtko
cs5376a 64 17. test bit stream generator the cs5376a test bit stream (tbs) generator cre- ates sine wave or impulse ? bit stream data to drive an external test dac. the tbs digital output can also be internally connected to the mdata in- puts for loopback testing of the digital filter. 17.1 pin descriptions tbsdata - pin 9 test bit stream 1-bit ? data output. tbsclk - pin 8 test bit stream clock output. not used by the cs4373 test dac. 17.2 tbs architecture the test bit stream generator consists of a data in- terpolator and a digital ? modulator. it receives periodic 24-bit data from the digital filter to create a 1-bit ? data output on the tbsdata pin. it also creates a clock signal at the data rate, output to the tbsclk pin. the tbs input data from the digital filter is scaled by the tbsgain register (0x2b). maximum stable amplitude is 0x04ffff, with 0x04b000 approxi- mately full scale for the cs4373 test dac. the full scale 1-bit ? output from the tbs generator is de- fined as 25% minimum and 75% maximum one?s density. 17.3 tbs configuration configuration options for the tbs generator are set through the tbscfg register (0x2a). gain scaling of the tbs generator output is set by the tbsgain register (0x2b). interpolation factor - intp[7:0] selects how many times the interpolator uses a data point when generating the output bit stream. inter- polation is zero based and represents one greater than the programmed register value. operational mode - tmode selects between sine wave or impulse output mode. clock rate - rate[2:0] selects the tbsdata and tbsclk output rate. synchronization - tsync enables synchronization of the tbs output phase to the msync signal. digital ? modulator 24-bit 1-bit tbsdata digital filter tbsgain register 24-bit figure 36. test bit stream generator block diagram data bus tbsclk clock generation tbscfg register
cs5376a 65 clock delay - cdly[2:0] programs a fractional delay for tbsclk with a 1/8 clock period resolution. loopback - loop enables digital loopback from the tbs output to the mdata inputs. run - run enables the test bit stream generator. data delay - ddly[5:0] programs full period delays for tbsdata, up to a maximum of 63 bits. gain - tbsgain[23:0] scales the amplitude of the sine wave output and generated impulse. maximum 0x04ffff, nominal 0x04b000. 17.4 tbs data source data to create test signals is loaded into digital fil- ter memory by configuration commands. the on- chip sine wave data is suitable for most tests, though custom data is required to support custom signal frequencies. see ?eeprom configuration commands? on page 28 or ?microcontroller con- figuration commands? on page 35 for information about programming tbs data. tbs rom data an on-chip 24-bit 1024 point digital sine wave is stored on the cs5376a. when selected by the ?write tbs rom data? configuration command, the tbs generator can produce the test signal fre- quencies listed in table 16. additional discrete test frequencies and output ra tes can be programmed with the on-chip data by varying the interpolation factor and output rate. test bit stream characteristic equation: (signal freq) * (# tbs data) * (interpolation + 1) = output rate example: (31.25 hz) * (1024) * (0x07 + 1) = 256 khz signal frequency (tbsdata) output rate (tbsclk) output rate selection (rate) interpolation selection (intp) 10.00 hz 256 khz 0x4 0x18 10.00 hz 512 khz 0x5 0x31 25.00 hz 256 khz 0x4 0x09 25.00 hz 512 khz 0x5 0x13 31.25 hz 256 khz 0x4 0x07 31.25 hz 512 khz 0x5 0x0f 50.00 hz 256 khz 0x4 0x04 50.00 hz 512 khz 0x5 0x09 125.00 hz 256 khz 0x4 0x01 125.00 hz 512 khz 0x5 0x03 table 16. tbs configurations using on-chip data
cs5376a 66 custom tbs data if a required test frequenc y cannot be generated us- ing the on-chip test bit stream data, a custom data set can be written into the cs5376a. the number of data points to write, up to a maximum of 1024, depends on the required test signal frequency, out- put rate, and available interpolation factors. cus- tom data sets must be continuous on the ends; i.e. when copied end-to-end the data set must produce a smooth curve. 17.5 tbs sine wave output when the tmode bit in the tbscfg register is low, the tbs generator operates in sine wave mode. in this mode, sine wa ve data from digital fil- ter memory is used to create a sine wave test signal that can drive a test dac. sine wave frequency and output data rate are calculated as shown by the characteristic equation of table 16. the sine wave maximum ? one?s density output from the tbs generator is set by the tbsgain register. tbsgain can be programmed up to a maximum of 0x04ffff, with the tbs generator unstable for higher amplitudes. for the cs4373 test dac, a gain value of 0x04b000 produces an ap- proximately full scale sine wave output (5 v pp dif- ferential). 17.6 tbs impulse output if the tmode bit in tbscfg is set high, the tbs generator operates in impul se mode. in this mode, the value in tbsgain sets the amplitude of the generated impulse. impulse amplitude and period are calculated as shown in table 17. to create an impulse from the tbs generator, the tbsgain register should be set to maximum, 0x04ffff, and the intp bits in tbscfg should also be set to maximum, 0xff. the rate bits should be set to produce data at the correct rate for the selected test dac. a rising edge on the timeb pin triggers the im- pulse output. when impulse mode is enabled but no timeb input is received, the tbs generator uses a negated tbsgain register as a repetitive input value. when a rising edge is recognized on the timeb pin, a single positive tbsgain value is written to the tbs generator to create the impulse. 17.7 tbs loopback testing included as part of the cs5376a test bit stream generator is a feedback path to the digital filter mdata inputs. this loopback mode provides a fully digital signal path to test the tbs generator, digital filter, and data collection interface. digital test bit stream impulse characteristics: interpolation selection (intp) output rate selection (rate) pulse width from cs4373 gain scale factor (tbsgain) pulse height from cs4373 0xff 0x5 500 s 0x04b000 860 mv 0xff 0x4 1 ms 0x04b000 820 mv 0xff 0x3 2 ms 0x04b000 820 mv 0x7f 0x5 250 s 0x04b000 820 mv 0x7f 0x4 500 s 0x04b000 820 mv 0x7f 0x3 1 ms 0x04b000 820 mv table 17. tbs impulse characteristics
cs5376a 67 loopback testing expects 512 khz ? data for the mdata inputs. a mismatch of the tbs generator full scale output and the mdata full scale input results in an am- plitude mismatch when testing in loopback mode. the tbs generator outputs a 75% maximum one?s density, while the mdata inputs expect an 86% maximum one?s density from a ? modulator, re- sulting in a measured full scale error of -3.6 db. 17.8 tbs synchronization when the tsync bit is set in the tbscfg regis- ter, the msync signal resets the sine wave data pointer and phase aligns the tbs signal output. once the digital filter is settled, all cs5376a de- vices receiving the sync signal will have identical tbs signal phase. see ?synchronization? on page 25 for more information about the sync and msync signals. if tsync is clear, msync has no effect on the tbs data pointer and no change in the tbs output phase will occur during synchronization.
cs5376a 68 18. time break controller a time break signal is used to mark timing events that occur during measurement. an external signal sets a flag in the status byte of an output sample to mark when the external event occurred. a rising edge input to the timeb pin causes the tb timing reference flag to be set in the sd port status byte. when set, the tb flag appears for only one output sample in the status byte of all enabled channels. the tb flag output can be delayed by programming a sample delay value into the time- brk digital filter register. 18.1 pin description timeb - pin 57 time break input pin, rising edge triggered. 18.2 time break operation an externally generated timing reference signal ap- plied to the timeb pin initiates an internal sample counter. after a number of output samples have passed, programmed in the timebrk digital filter register (0x29), the tb flag is set in the status byte of the sd port output word for all enabled channels. the tb flag is automatically cleared for subse- quent data words, and appears for only one output sample in each channel. 18.3 time break delay the timebrk register (0x29) sets a sample delay between a received rising edge on the timeb pin and writing the tb flag into the sd port status byte. the programmable sample counter can compensate for group delay through the digital filters. when the proper group delay value is programmed into the timebrk register, the tb flag will be set in the status byte of the measurement sample taken when the timing reference signal was received. 18.3.1 step input and group delay a simple method to empirically measure the step response and group delay of a cs5376a measure- ment channel is to use the time break signal as both a timing reference input and an analog step input. when a rising edge is received on the timeb pin with no delay programmed into the timebrk reg- ister, the tb flag is set in the next sd port status byte. the same rising edge can act as a step input to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. by comparing the timing of the tb status flag output and the rising edge in the measurement data, the measurement channel group delay can be deter- mined. timeb in sd port status byte delay counter timebrk tb flag figure 37. time break block diagram
cs5376a 69 19. general purpose i/o the general purpose i/o (gpio) block provides 12 general purpose pins to interface with external hardware. 19.1 pin descriptions gpio[4:0]:cs[4:0] - pins 32 - 36 standard gpio pins also used as spi 2 chip selects. gpio[5:10] - pins 37, 41 - 45 standard gpio pins. gpio11:eecs - pin 46 standard gpio pin also used as an spi 1 chip select when booting from an external eeprom. 19.2 gpio architecture each gpio pin can be configured as input or out- put, high or low, with a weak (~200 k ? ) internal pull-up resistor enabled or disabled. several gpio pins also double as chip selects for the spi 1 and spi 2 serial ports. figure 38 shows the structure of a bi-directional gpio pin with spi chip select func- tionality. when the cs5376a is used as an spi master, either when booting from eeprom using spi 1 or per- forming master mode transactions using spi 2, the chip select signals from spi 1 and spi 2 are logi- cally and-ed with the gpio data bit. the corre- sponding gpio pin should be initialized as output mode and logical 1 to produce the chip select fall- ing edge. 19.3 gpio registers when used as standard gpio pins, settings are pro- grammed in the gpcfg0 and gpcfg1 registers. gp_dir bits set the input/output mode, gp_pull bits enable/disable the internal pull-up resistor, and gp_data bits set the output data value. after re- set, gpio pins default as inputs with pull-up resis- tors enabled. 19.4 gpio input mode when reading a value from the gp_data bits, the returned data reports the current state of the pins. if a pin is externally driven high it reads a logical 1, if externally driven low it reads a logical 0. when a gpio pin is used as an input, the pull-up resistor should be disabled to save power if it isn?t required. 19.5 gpio output mode when a gpio pin is programmed as an output with a data value of 0, the pin is driven low and the in- ternal pull-up resistor is automatically disabled. when programmed as an output with a data value of 1, the pin is driven high and the pull-up resistor is inconsequential. figure 38. gpio bi-directional structure cs output from spi gpio/cs gp_dir data bit gp_data gp_pull pull up logic r
cs5376a 70 any gpio pin can be used as an open-drain output by setting the data value to 0, enabling the pull-up, and using the gp_dir direction bits to control the pin value. this open-drain output configuration uses the internal pull-up resistor to hold the pin high when gp_dir is set as an input, and drives the pin low when gp_dir is set as an output. 19.5.1 gpio reads in output mode when reading gpio pins the gp_data register value always reports the current state of the pins, so a value written in output mode does not necessarily read back the same value. if a pin in output mode is written as a logical 1, the cs5376a attempts to drive the pin high. if an external device forces the pin low, the read value reflects the pin state and re- turns a logical 0. similarly, if an output pin is writ- ten as a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. in both cases the cs5376a is in contention with the external device resulting in increased power consumption.
cs5376a 71 20. serial peripheral interface 2 the serial peripheral interface 2 (spi 2) port is a master mode spi port designed to interface with se- rial peripherals. by writing the spi2 digital filter registers, multiple serial slave devices can be con- trolled through the cs5376a. 20.1 pin descriptions cs[4:0] - pins 32 - 36 serial chip selects. multiplexed with gpio pins. sck2 - pin 31 serial clock output, common to all channels. so - pin 30 serial data output, co mmon to all channels. si[4:1] - pins 26 - 29 serial data inputs. 20.2 spi 2 architecture the spi 2 pin interface has multiple chip selects and serial data inputs, but a common serial clock and serial data output. which chip select and serial input to use for a particular slave serial transaction is selected by bits in the spi2ctrl digital filter register. spi 2 chip select outputs are multiplexed with gpio pins, which cannot perform both functions simultaneously. when used as a chip select, the gpio output must be programmed high to permit the chip select to operate as an active low signal. see ?general purpose i/o? on page 69 for informa- tion about programming the gpio pins. the spi 2 interface transfers data from the spi 2 registers to a slave serial device and back through a bi-directional 8-bit shift register. serial transac- tions are automatic once control, command, and data values are written into the spi 2 digital filter registers. 20.3 spi 2 registers spi 2 transactions are initiated by first writing command, address, and data values to the spi2cmd and spi2dat digital filter registers, and then writing the spi2ctrl register to set the d2sreq bit. the d2sreq bit initiates a serial figure 39. serial peripheral interface 2 (spi 2) block diagram sck2 si4 so cs1 cs2 cs3 cs4 pin logic select to gpio block si2 si1 si3 logic spi2en[4:1] / rch[1:0] 4:1 cs0 digital filter cs[4:0] sckfs[2:0] / sckpo / sckph
cs5376a 72 transaction using the programmed spi2ctrl con- figuration. 20.3.1 spi 2 control register the spi 2 hardware is configured by the spi2ctrl digital filter register (0x10). bits in this register select the serial input pin and chip select pin used for a transaction, set the total number of bytes in a transaction, initiate a serial transaction, and report status information about a transaction. other bits in spi2ctrl set hardware configuration options such as the serial clock rate, the spi mode, and the state of internal pull-up re- sistors. chip select enable - cs[4:0] the chip select pin to use during a transaction is se- lected by the cs0, cs1, cs2, cs3, and cs4 bits. multiple chip selects can be enabled to send a transaction to more than one serial peripheral. serial input select - spi2en[4:1], rch[1:0] which serial input pin will receive data is selected using the spi2en bits and the rch bits. the spi2en bits enable the serial input, while the rch bits select it for the spi 2 transaction. a channel?s spi2en bit should always be enabled, even when transactions do not expect to receive data from the slave device. transaction bytes - dnum[2:0] dnum bits specify the total number of bytes to transfer during a serial transaction, including com- mand and address bytes. dnum is zero based and represents one greater than the number pro- grammed. serial clock rate - sckfs[2:0] the serial clock rate output from the sck2 pin is selected by the sckfs bits. serial clock rates range from 32 khz to 4.096 mhz. spi mode - sckpo, sckph the serial mode used for a transaction depends on the sckpo and sckph bits. the spi 2 port sup- ports all four spi modes, with mode 0 and mode 3 the most commonly used. supported modes are: spi mode 0 (0,0): sckpo = 0, sckph = 0 spi mode 1 (0,1): sckpo = 0, sckph = 1 spi mode 2 (1,0): sckpo = 1, sckph = 0 spi mode 3 (1,1): sckpo = 1, sckph = 1 wired-or mode - wom the spi 2 pins can operate in two modes depend- ing on the wom bit. a default push-pull configu- ration drives output signals both high and low. wired-or mode only drives low, relying on a weak internal pull-up resistor to pull the output high. wired-or mode permits multiple serial controllers to access the same bus without contention. initiating serial transactions - d2sreq writing the d2sreq bit starts an spi 2 serial transaction. when complete, the d2sreq bit is au- tomatically cleared by the spi 2 hardware. status and error bits - d2sop, swef, tm three bits in the spi2ctrl register report status and error information. d2sop is set when the spi 2 port is busy perform- ing a transaction. it is automatically cleared when the transaction is completed. swef is set if a request to initiate a new transac- tion occurs during the current transaction. this flag is latched and must be cleared manually. tm is set to indicate the spi 2 port timed out on the requested transaction. this flag is latched and must be cleared manually. 20.3.2 spi 2 command register the spi2cmd register (0x11) is a 16-bit digital fil- ter register with the high byte designated as an spi
cs5376a 73 command and the low byte designated as an ad- dress. the high byte holds an 8-bit spi ?write? or ?read? opcode, as shown in figure 40, and the low byte holds an 8-bit serial address. during a transaction, bits in spi2cmd are output msb first, with data in spi2dat written or read following. 20.3.3 spi 2 data register the spi2dat register (0x12) is a 24-bit digital fil- ter register containing three spi data bytes. data in spi2dat is always lsb aligned, with 1-byte data written or received using the low byte, 2-byte data written or received using the middle and low bytes, and 3-byte data written or received using all three bytes. data in spi2dat is written or read after writing the command and address bytes from the spi2cmd register. 20.4 spi 2 transactions the spi 2 port operates as an spi master to perform write and read transactions with serial slave periph- erals. the exact format of the spi transactions de- pends on the spi mode, selected using the sckpo and sckph bits in the spi2ctrl register. write transactions write transactions start by writing an spi ?write? (0x02) opcode and an 8-bit destination address into the spi2cmd register and the output data value to the spi2dat register. writing the d2sreq bit in the spi2ctrl register initiates the spi 2 transac- tion based on the spi2ctrl configuration. a write transaction outputs 1 or 2 bytes from the spi2cmd register followed by 1, 2, or 3 bytes from the spi2dat register. write transactions are therefore a minimum of 1 byte (dnum = 0) and a maximum of 5 bytes (dnum = 4). the spi 2 port uses the dnum bits in the spi2ctrl register to determine the total number of bytes to send during a write transaction. write transactions are not required to use standard spi commands. if serial peripherals use non-stan- dard write commands they can be written into spi2cmd and spi2dat as required. read transactions read transactions start by writing an spi ?read? (0x03) opcode and an 8-bit source address to the spi2cmd register. writing the d2sreq bit in the spi2ctrl register initiates the spi 2 transaction based on the spi2ctrl configuration, with the data value automatically received into the spi2dat register. a read transaction outputs 2 bytes from the spi2cmd register and can receive 1, 2, or 3 bytes into the spi2dat register. read transactions are a minimum of 3 bytes (dnum = 2) and a maximum of 5 bytes (dnum = 4). the spi 2 port uses the dnum bits in the spi2ctrl register to determine the total number of bytes to send and receive during a read transaction. read transactions are not required to use standard spi commands. if serial peripherals use non-stan- dard read commands they can be written to the spi2cmd register, as long as they conform to the format of 2 bytes out with 1, 2, or 3 bytes in. spi modes the spi mode for the spi 2 port is selected in the spi2ctrl register using the sckpo and sckph bits. the most commonly used spi modes are mode 0 and mode 3, both of which define the serial clock with data valid on rising edges and transition- ing on falling edges. in spi mode 0, the sck2 serial clock is defined ini- tially in a low state. output data on the so pin is valid immediately after the chip select pin goes low, and the first rising e dge of sck2 latches valid data.
cs5376a 74 in spi mode 3, the sck2 serial clock is defined ini- tially in a high state. output data on the so pin is invalid until the initial falling edge of sck2, and the first rising edge of sck2 latches valid data. spi modes 1 and 4 work similarly to modes 0 and 3, with the serial clock de fined to have data valid on falling edges and transitioning on rising edges. figure 40. spi 2 master mode transactions so 0x02 addr data1 si so si spi 2 write to external slave spi 2 read from external slave data3 data2 0x03 addr data1 data3 data2 cs cs spi2cmd[15:8] spi2cmd[7:0] spi2dat spi2cmd[15:8] spi2cmd[7:0] spi2dat instruction opcode address definition write 0x02 spi2cmd[7:0] write serial peripheral beginning at the address given in spi2cmd[7:0]. read 0x03 spi2cmd[7:0] read serial peripheral beginning at the address given in spi2cmd[7:0].
cs5376a 75 sck2 so figure 41. spi 2 transaction details cs msb lsb sck2 si sckpo = 0 sckpo = 1 x 61 2 3 4 5 lsb msb 6 1 2 3 4 5 18 27 6 5 4 3 cycle slave devices only drive si after being selected and responding to a read command. sck2 so cs msb lsb sck2 si sckpo = 0 sckpo = 1 x 61 2 3 4 5 msb lsb 61 2 3 4 5 18 27 6 5 4 3 cycle slave devices only drive si after being selected and responding to a read command. spi 2 transaction with sckph=0 spi 2 transaction with sckph=1
cs5376a 76 21. boundary scan jtag the cs5376a includes an ieee 1149.1 boundary scan jtag port to test pcb interconnections. refer to the ieee 1149.1 specification for more informa- tion about boundary scan testing. 21.1 pin descriptions trst - pin 1 reset input for the test access port (tap) controller and all boundary scan cells, active low. connect to gnd to disable the jtag port. tms - pin 2 serial input to select the jtag test mode. tck - pin 3 clock input to the tap controller. tdi - pin 4 serial input to the scan chain or tap controller. tdo - pin 5 serial output from the scan chain or tap control- ler. 21.2 jtag architecture the jtag test circuitry consists of a test access port (tap) controller and boundary scan cells con- nected to each pin. the boundary scan cells are linked together to create a scan chain around the cs5376a. 21.2.1 jtag reset as required by the ieee 1149.1 specification, the jtag trst signal is independent of the cs5376a reset signal. in systems not using the jtag port, trst should be connected to ground. in systems using the jtag port, trst and reset should be independently driven to provide reset capability during boundry scan. 21.2.2 tap controller the test access port (tap) controller manages commands and data through the boundary scan chain. it supports the four jtag instructions and contains the idcode listed in table 18. the tap controller also implements the 16 jtag state assignments from the ieee 1149.1 specifica- tion, which are sequenced using tms and tck. figure 42. jtag block diagram tdi tdo controller ta p trst tms tck boundary scan cells
cs5376a 77 21.2.3 boundary scan cells the cs5376a jtag test port provides access to all device pins via internal boundary scan cells. when the jtag port is disabled, boundary scan cells are transparent and do not affect cs5376a operation. when the jtag port is enabled, boundary scan cells can write and read each pin independent of cs5376a operation. boundary scan cells are serially linked to create a scan chain around the cs5376a controlled by the tap controller. table 19 lists the scan cell map- ping of the cs5376a. jtag instructions encoding bypass 11 extest 00 idcode 01 sample / preload 10 jtag idcode components encoding revision 0x10000000 device id 0x05376000 manufacturer id 0x000000c9 cs5376a idcode 0x153760c9 table 18. jtag instructions and idcode
cs5376a 78 brc pin function brc pin function brc pin function 1 tbsclk data out 36 gpio3 data in 68 gpio11 data in 2 tbsdata data out 37 data out 69 data out 3 dnc data out 38 output enable 70 output enable 4 mclk/2 data out 39 pullup 71 pullup 5 mclk data out 40 gpio4 data in 72 sso data out 6 msync data out 41 data out 73 output enable 7 mdata4 data in 42 output enable 74 wom 8 mflag4 data in 43 pullup 75 sck1 data in 9 mdata3 data in 44 gpio5 data in 76 data out 10 mflag3 data in 45 data out 77 output enable 11 mdata2 data in 46 output enable 78 wom 12 mflag2 data in 47 pullup 79 pullup 13 mdata1 data in 48 gpio6 data in 80 ssi data in 14 mflag1 data in 49 data out 81 miso data in 15 gnd data in 50 output enable 82 data out 16 si4 data in 51 pullup 83 output enable 17 si3 data in 52 gpio7 data in 84 wom 18 si2 data in 53 data out 85 pullup 19 si1 data in 54 output enable 86 mosi data in 20 so data out 55 pullup 87 data out 21 wom 56 gpio8 data in 88 output enable 22 sck2 data out 57 data out 89 wom 23 wom 58 output enable 90 pullup 24 gpio0 data in 59 pullup 91 sint data out 25 data out 60 gpio9 data in 92 reset data in 26 output enable 61 data out 93 boot data in 27 pullup 62 output enable 94 timeb data in 28 gpio1 data in 63 pullup 95 clk data in 29 data out 64 gpio10 data in 96 sync data in 30 output enable 65 data out 97 sddat data out 31 pullup 66 output enable 98 output enable 32 gpio2 data in 67 pullup 99 sdrdy data out 33 data out 100 sdclk data in 34 output enable 101 sdtko data out 35 pullup 102 sdtki data in table 19. jtag scan cell mapping
cs5376a 79 22. revision history the cs5376a is a pin compatible upgrade to the cs5376. the part family has had three revisions: cs5376 rev a cs5376 rev b cs5376a rev a the part number change for cs5376a reflects ad- ditional functionality built into the device. 22.1 changes from cs5376 rev a to cs5376 rev b new sinc filter, sinc3 added a new sinc filter, sinc3, between the previ- ous sinc filters and fir1. will permit higher deci- mation rates for seismology applications. not used for 0.25 ms, 0.5 ms, 1 ms, or 2 ms output rates to maintain backward compatibility. added fir1 coefficients included an improved fir1 filter to compensate for sinc filter droop. previous filter had stop band fre- quency components up to -100 db not removed by the fir2 brick wall filter. required stop band at- tenuation is 130 db minimum. previous fir1 filter coefficients still included to maintain backwards compatibility. added iir coefficients included 3 hz iir1 and iir2 filter coefficients for the 0.5 ms, 1 ms, 2 ms, 3 ms, and 4 ms configura- tions (5 sets iir1, 5 sets iir2). previous 2 hz @ 1 ms coefficient set was removed. modified output word rate selection changed the dec bit settings in the filtcfg reg- ister used to select an output word rate. re-num- bered to include the new 120 hz, 60 hz, 30 hz, 15 hz, and 7.5 hz output rates. other settings the same for backward compatibility. modified rom coefficient selection method changed the rom coefficient selection routines (spi and eeprom) to require a 24 bit data word. previously no data word was required, only the command byte. the data word is parsed to select the fir1, fir2, iir1, and iir2 coefficient sets. modified rom tbs data selection method changed the rom test bit stream selection routine (spi and eeprom) to require a 24 bit data word. previously no data word was required, only the command byte. the data word scales the rom test bit stream data to a user selected amplitude. modified spi port to strobe sint pin the spi port now pulses the sint pin whenever data is received. can be used by a microcontroller to trigger additional data writes. eliminates the need to poll the e2dreq bit. fixed continuous synchronization operation the synchronization operation was modified to permit continuous re-sync. the sd port fifo is no longer reset by the sync interrupt. corrected eeprom loader bug the eeprom loader bug is fixed. a preamble to write required constants into memory is no longer required. 22.2 changes from cs5376 rev b to cs5376a rev a fixed synchronization repeatability bug identical synchronization signals previously caused different impulse responses from multi- ple devices. synchronization is now repeatable.
cs5376a 80 modified sinc2 filter to correct gain and tim- ing errors corrected sinc2 decimate by 2 gain error which affected 4000 sps operation. also mod- ified sinc2 decimate by 16 output timing to match output of other sinc2 rates. previous sinc2 decimate by 16 output was one sample later than expected. corrected gain error of 333 sps output rate sinc architecture was modified to correct gain error in sinc2 decimate by 12 by moving dec- imate by 3 stage into sinc3. modified sinc3 filter for new low bandwidth rates. newly supported output word rates are 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 sps. older low bandwidth rates of 120, 60, 30, 15, 7.5 sps were removed. no changes to 4000, 2000, 1000, 500, 333, 250 sps rates for backwards compatibility to cs5376 revision a/b. added minimum phase fir coefficients minimum phase fir1 coefficient set 1 and fir2 coefficient set 1 are newly available as se- lections for the spi and eeprom 'write rom coefficients' command. corrected iir2/iir3 channels 2, 3, 4 bug when selecting iir2 or iir3 output, data from channels 2, 3, and 4 were corrupted. iir2 and iir3 now operate correctly for these channels. corrected iir2 coefficient dc offset iir2 coefficient sets 0, 1, and 3 did not perfect- ly cancel dc due to coefficient b20, b21, b22 mismatch. new b21 iir2 coefficients correct this offset error. removed gain scale factor from 'write tbs rom' command tbs data was previously scaled during config- uration by a data word following the 'write tbs rom' command. added a new tbsgain register (0x2b, replacing wd_cfg) that scales the tbs amplitude and can be modified during normal operation. removed watchdog timer the watchdog timer was removed. replaced wd_cfg register (0x2b) with tbsgain reg- ister. set gpio11 as tri-state when eeprom boot completed after stand-alone boot from eeprom, gpio11 (acting as eeprom chip select) was previously driven high. this pin now tri-states with an internal pull-up to hold it high. modified test bit stream (tbs) to disable loopback when tbs disabled. if tbs loopback mode was enabled, the exter- nal mdata inputs were disconnected from the sinc filter even if the tbs was disabled. now when the tbs is disabled, loopback mode is automatically disabled also. added test bit stream (tbs) impulse mode. tbs can now operate in sine wave or impulse mode, depending on bit 15 in the tbscfg reg- ister. when impulse mode is enabled (tbscfg bit 15 = 1), a rising edge on the timeb pin causes the tbs to output an impulse bitstream. when sine wave mode is enabled (tbscfg bit 15 = 0), operation is identical to cs5376 revi- sion a/b.
cs5376a 81 added test bit stream (tbs) synchronization in sine wave mode. the tbs sine wave phase will reset if bit 11 of the tbscfg register is set (tbscfg bit 11 = 1) and a rising edge is received on the sync pin. when tbscfg bit 11 is set low (tbscfg bit 11 = 0), tbs phase is unaffected by the sync input similar to cs5376 revision a/b. modified time break delay function. the timing delay between receiving a rising edge on the timeb pin and asserting the timeb flag in the output word status bits is corrected. in cs5376 revision a/b a '0' value in the timebreak register (0x29) disabled the timeb status bit write, and a '1' value set the status bit in the current output word. now, a '0' value sets the timeb status bit in the current output word, and a '1' value delays until the fol- lowing word.
cs5376a 82 23. register summary 23.1 spi 1 registers the cs5376a spi 1 registers interface the serial port to the digital filter. name addr. type # bits description spi1ctrlh 00 r/w 8 spi 1 control register, high byte spi1ctrlm 01 r/w 8 spi 1 control register, middle byte spi1ctrll 02 r/w 8 spi 1 control register, low byte spi1cmdh 03 r/w 8 spi 1 command, high byte spi1cmdm 04 r/w 8 spi 1 command, middle byte spi1cmdl 05 r/w 8 spi 1 command, low byte spi1dat1h 06 r/w 8 spi 1 data 1, high byte spi1dat1m 07 r/w 8 spi 1 data 1, middle byte spi1dat1l 08 r/w 8 spi 1 data 1, low byte spi1dat2h 09 r/w 8 spi 1 data 2, high byte spi1dat2m 0a r/w 8 spi 1 data 2, middle byte spi1dat2l 0b r/w 8 spi 1 data 2, low byte
cs5376a 83 23.1.1 spi1ctrl : 0x00, 0x01, 0x02 (msb) 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- r/w r/w1 r/w r/w r/w r/w r/w r/w 00001011 15 14 13 12 11 10 9 8 smodf -- -- emop swef -- -- e2dreq r r/w r r r r/w r/w r/w 00000010 7654321(lsb) 0 -- -- -- -- -- -- -- -- r/w r/w r/w r/w r/w r/w r/w r/w 00100000 spi 1 address: 0x00 0x01 0x02 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: 23:16 -- reserved 15 smodf spi 1 mode fault flag 7:0 -- reserved 14:13 -- reserved 12 emop external master to spi 1 operation in progress flag 11 swef spi 1 write collision error flag 10:9 -- reserved 8 e2dreq external master to digital filter request flag figure 43. spi 1 control register spi1ctrl
cs5376a 84 23.1.2 spi1cmd : 0x03, 0x04, 0x05 (msb) 23 22 21 20 19 18 17 16 s1cmd23 s1cmd22 s1cmd21 s1cmd20 s1cmd19 s1cmd18 s1cmd17 s1cmd16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 s1cmd15 s1cmd14 s1cmd13 s1cmd12 s1cmd11 s1cmd10 s1cmd9 s1cmd8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 s1cmd7 s1cmd6 s1cmd5 s1cmd4 s1cmd3 s1cmd2 s1cmd1 s1cmd0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 spi 1 address: 0x03 0x04 0x05 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 44. spi 1 command register spi1cmd bit definitions: 23:16 s1cmd[23:16] spi 1 command high byte 15:8 s1cmd[15:8] spi 1 command middle byte 15:8 s1cmd[7:0] spi 1 command low byte
cs5376a 85 23.1.3 spi1dat1 : 0x06, 0x07, 0x08 (msb) 23 22 21 20 19 18 17 16 s1dat23 s1dat22 s1dat21 s1dat20 s1dat19 s1dat18 s1dat17 s1dat16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 s1dat15 s1dat14 s1dat13 s1dat12 s1dat11 s1dat10 s1dat9 s1dat8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 s1dat7 s1dat6 s1dat5 s1dat4 s1dat3 s1dat2 s1dat1 s1dat0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 spi 1 address: 0x06 0x07 0x08 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 45. spi 1 data register spi1dat1 bit definitions: 23:16 s1dat[23:16] spi 1 data high byte 15:8 s1dat[15:8] spi 1 data middle byte 15:8 s1dat[7:0] spi 1 data low byte
cs5376a 86 23.1.4 spi1dat2 : 0x09, 0x0a, 0x0b (msb) 23 22 21 20 19 18 17 16 s1dat23 s1dat22 s1dat21 s1dat20 s1dat19 s1dat18 s1dat17 s1dat16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 s1dat15 s1dat14 s1dat13 s1dat12 s1dat11 s1dat10 s1dat9 s1dat8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 s1dat7 s1dat6 s1dat5 s1dat4 s1dat3 s1dat2 s1dat1 s1dat0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 spi 1 address: 0x09 0x0a 0x0b -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 46. spi 1 data register spi1dat2 bit definitions: 23:16 s1dat[23:16] spi 1 data high byte 15:8 s1dat[15:8] spi 1 data middle byte 15:8 s1dat[7:0] spi 1 data low byte
cs5376a 87 23.2 digital filter registers the cs5376a digital filter registers control ha rdware peripherals and filtering functions. name addr. type # bits description config 00 r/w 24 hardware configuration reserved 01-0d r/w 24 reserved gpcfg0 0e r/w 24 gpio[7:0] direction, pull-up enable, and data gpcfg1 0f r/w 24 gpio[11:8] direction, pull-up enable, and data spi2ctrl 10 r/w 24 spi2 control spi2cmd 11 r/w 16 spi2 command spi2dat 12 r/w 24 spi2 data reserved 13-1f r/w 24 reserved filtcfg 20 r/w 24 digital filter configuration gain1 21 r/w 24 gain correction channel 1 gain2 22 r/w 24 gain correction channel 2 gain3 23 r/w 24 gain correction channel 3 gain4 24 r/w 24 gain correction channel 4 offset1 25 r/w 24 offset correction channel 1 offset2 26 r/w 24 offset correction channel 2 offset3 27 r/w 24 offset correction channel 3 offset4 28 r/w 24 offset correction channel 4 timebrk 29 r/w 24 time break delay tbscfg 2a r/w 24 test bit stream configuration tbsgain 2b r/w 24 test bit stream gain system1 2c r/w 24 user defined system register 1 system2 2d r/w 24 user defined system register 2 version 2e r/w 24 hardware version id selftest 2f r/w 24 self-test result code
cs5376a 88 23.2.1 config : 0x00 (msb)2322212019181716 -- -- -- -- -- dfs2 dfs1 dfs0 r/w r/w r/w r/w r/w r/w r/w r/w 00000101 15 14 13 12 11 10 9 8 -- -- -- -- -- mckfs2 mckfs1 mckfs0 r/w r/w r/w r/w r/w r/w r/w r/w 00000100 7654321(lsb)0 -- -- mcken2 mcken mdifs -- boot msen r/w r/w r/w r/w r/w r/w r r/w 00000001 figure 47. hardware configuration register config bit definitions: 23:19 -- reserved 15:11 -- reserved 7:6 -- reserved 18:16 dfs [2:0] digital filter frequency select 111: 16.384 mhz 110: 8.192 mhz 101: 4.096 mhz 100: 2.048 mhz 011: 1.024 mhz 010: 512 khz 001: 256 khz 000: 32 khz 10:8 mckfs [2:0] mclk frequency select 111: reserved 110: reserved 101: 4.096 mhz 100: 2.048 mhz 011: 1.024 mhz 010: 512 khz 001: reserved 000: reserved 5 mcken2 mclk/2 output enable 1: enabled 0: disabled 4 mcken mclk output enable 1: enabled 0: disabled 3 mdifs mdata input frequency select 1: 256 khz 0: 512 khz 2 -- reserved 1 boot boot source indicator 1: booted from eeprom 0: booted from micro 0 msen msync enable 1: msync generated 0: msync remains low df address: 0x00 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition
cs5376a 89 23.2.2 gpcfg0 : 0x0e (msb) 23 22 21 20 19 18 17 16 gp_dir7 gp_dir6 gp_dir5 gp_dir4 gp_dir3 gp_dir2 gp_dir1 gp_dir0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 gp_pull7 gp_pull6 gp_pull5 gp_pull4 gp_pull3 gp_pull2 gp_pull1 gp_pull0 r/w r/w r/w r/w r/w r/w r/w r/w 11111111 7654321(lsb) 0 gp_data7 gp_data6 gp_data5 gp_data4 gp_data3 gp_data2 gp_data1 gp_data0 r/w r/w r/w r/w r/w r/w r/w r/w 11111111 df address: 0x0e -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: note: gpio[4:0] also used as spi 2 chip selects cs[4:0]. 23:16 gp_dir [7:0] gpio pin direction 1: output 0: input 15:8 gp_pull [7:0] gpio pullup resistor 1: enabled 0: disabled 7:0 gp_data [7:0] gpio data value 1: vdd 0: gnd figure 48. gpio configuration register gpcfg0
cs5376a 90 23.2.3 gpcfg1 : 0x0f (msb) 23 22 21 20 19 18 17 16 -- -- -- -- gp_dir11 gp_dir10 gp_dir9 gp_dir8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 -- -- -- -- gp_pull11 gp_pull10 gp_pull9 gp_pull8 r/w r/w r/w r/w r/w r/w r/w r/w 00001111 7654321(lsb) 0 -- -- -- -- gp_data11 gp_data10 gp_data9 gp_data8 r/w r/w r/w r/w r/w r/w r/w r/w 00001111 df address: 0x0f -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: note: gpio11 also used as boot eeprom chip select eecs. 23:20 -- reserved 15:12 -- reserved 7:4 -- reserved 19:16 gp_dir [11:8] gpio pin direction 1: output 0: input 11:8 gp_pull [11:8] gpio pullup resistor 1: enabled 0: disabled 3:0 gp_data [11:8] gpio data value 1: vdd 0: gnd figure 49. gpio configuration register gpcfg1
cs5376a 91 23.2.4 spi2ctrl : 0x10 (msb) 23 22 21 20 19 18 17 16 wom sckfs2 sckfs1 sckfs0 spi2en3 spi2en2 spi2en1 spi2en0 r/w r/w r/w r/w r/w r/w r/w r/w 00111111 15 14 13 12 11 10 9 8 rch1 rch0 d2sop sckph swef sckpo tm d2sreq r/w r/w r r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 dnum2 dnum1 dnum0 cs4 cs3 cs2 cs1 cs0 r/w r/w r/w r/w r/w r/w r/w r/w 11100000 df address: 0x10 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition. bit definitions: 23 wom wired-or mode 1: enabled (open drain) 0: disabled (push-pull) 15:14 rch [1:0] read channel 11: si4 10: si3 01: si2 00: si1 7:5 dnum [2:0] number of bytes in serial transaction 22:20 sckfs [2:0] sck2 frequency select 111: reserved 110: reserved 101: 4.096 mhz 100: 2.048 mhz 011: 1.024 mhz 010: 512 khz 001: 128 khz 000: 32 khz 13 d2sop digital filter to spi2 operation in progress flag 4 cs4 chip select 4 enable 12 sckph so output timing 1: data becomes valid on first sck2 edge 0: data becomes valid before first sck2 edge 3 cs3 chip select 3 enable 2 cs2 chip select 2 enable 11 swef spi2 write collision flag 1 cs1 chip select 1 enable 19:16 spi2en [3:0] si[4:1] input enable 1111: all enabled 0000: all disabled 10 sckpo sck2 data polarity 1: valid on falling edge, transition on rising edge 0: valid on rising edge, transition on falling edge 0 cs0 chip select 0 enable 9 tm spi2 timeout flag 1: spi2 timed out 0: not timed out 8 d2sreq digital filter to spi2 serial transaction request 1: request operation 0: operation complete (cleared by hardware) figure 50. spi 2 control register spi2ctrl
cs5376a 92 23.2.5 spi2cmd : 0x11 (msb) 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 scmd15 scmd14 scmd13 scmd12 scmd11 scmd10 scmd9 scmd8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 scmd7 scmd6 scmd5 scmd4 scmd3 scmd2 scmd1 scmd0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x11 -- not defined; read as 0 rreadable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: 23:16 -- reserved 15:8 scmd[15:8] spi2 upper command byte 15:8 scmd[7:0] spi2 lower command byte figure 51. spi 2 command register spi2cmd
cs5376a 93 23.2.6 spi2dat : 0x12 (msb) 23 22 21 20 19 18 17 16 sdat23 sdat22 sdat21 sdat20 sdat19 sdat18 sdat17 sdat16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 sdat15 sdat14 sdat13 sdat12 sdat11 sdat10 sdat9 sdat8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 sdat7 sdat6 sdat5 sdat4 sdat3 sdat2 sdat1 sdat0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x12 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 52. spi 2 data register spi2dat bit definitions: 23:16 sdat[23:16] spi2 upper data byte 15:8 sdat[15:8] spi2 middle data byte 15:8 sdat[7:0] spi2 lower data byte
cs5376a 94 23.2.7 filtcfg : 0x20 (msb) 23 22 21 20 19 18 17 16 -- -- -- exp4 exp3 exp2 exp1 exp0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 -- orcal useor usegr -- fsel2 fsel1 fsel0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 dec3 dec2 dec1 dec0 -- -- ch1 ch0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x20 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: 23:21 -- reserved 15 -- reserved 7:4 dec[3:0] decimation selection (output word rate) 20:16 exp[4:0] offset calibration exponent 14 orcal run offset calibration 1: enable 0: disable 0111: 4000 sps 0110: 2000 sps 0101: 1000 sps 0100: 500 sps 0011: 333 sps 13 useor use offset correction 1: enable 0: disable 0010: 250 sps 0001: 200 sps 0000: 125 sps 1111: 100 sps 1110: 50 sps 12 usegr use gain correction 1: enable 0: disable 1101: 40 sps 1100: 25 sps 1011: 20 sps 1010: 10 sps 1001: 5 sps 1000: 1 sps 11 -- reserved 3:2 -- reserved 10:8 fsel[2:0] output filter stage select 111: reserved 110: reserved 101: iir 3rd order 100: iir 2nd order 011: iir 1st order 010: fir2 output 001: fir1 output 000: sinc output 1:0 ch[1:0] channel enable 11: 3 channel (1, 2, 3) 10: 2 channel (1, 2) 01: 1 channel (1 only) 00: 4 channel (1, 2, 3, 4) figure 53. filter configuration register filtcfg
cs5376a 95 23.2.8 gain1 - gain4 : 0x21 - 0x24 (msb) 23 22 21 20 19 18 17 16 gain23 gain22 gain21 gain20 gain19 gain18 gain17 gain16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 gain15 gain14 gain13 gain12 gain11 gain10 gain9 gain8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 gain7 gain6 gain5 gain4 gain3 gain2 gain1 gain0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x21 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 54. gain correction register gain1 bit definitions: 23:16 gain[23:16] gain correction upper byte 15:8 gain[15:8] gain correction middle byte 15:8 gain[7:0] gain correction lower byte
cs5376a 96 23.2.9 offset1 - offset4 : 0x25 - 0x28 (msb) 23 22 21 20 19 18 17 16 ofst23 ofst22 ofst21 ofst20 ofst19 ofst18 ofst17 ofst16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 ofst15 ofst14 ofst13 ofst12 ofst11 ofst10 ofst9 ofst8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 ofst7 ofst6 ofst5 ofst4 ofst3 ofst2 ofst1 ofst0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x25 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 55. offset correction register offset1 bit definitions: 23:16 ofst[23:16] offset correction upper byte 15:8 ofst[15:8] offset correction middle byte 15:8 ofst[7:0] offset correction lower byte
cs5376a 97 23.2.10 timebrk : 0x29 (msb) 23 22 21 20 19 18 17 16 tbrk23 tbrk22 tbrk21 tbrk20 tbrk19 tbrk18 tbrk17 tbrk16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 tbrk15 tbrk14 tbrk13 tbrk12 tbrk11 tbrk10 tbrk9 tbrk8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 tbrk7 tbrk6 tbrk5 tbrk4 tbrk3 tbrk2 tbrk1 tbrk0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x29 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 56. time break counter register timebrk bit definitions: 23:16 tbrk[23:16] time break counter upper byte 15:8 tbrk[15:8] time break counter middle byte 15:8 tbrk[7:0] time break counter lower byte
cs5376a 98 23.2.11 tbscfg : 0x2a (msb) 23 22 21 20 19 18 17 16 intp7 intp6 intp5 intp4 intp3 intp2 intp1 intp0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 tmode rate2 rate1 rate0 tsync cdly2 cdly1 cdly0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 loop run ddly5 ddly4 ddly3 ddly2 ddly1 ddly0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x2a -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 57. test bit stream configuration register tbscfg bit definitions: 23:16 intp[7:0] interpolation factor 0xff: 256 0xfe: 255 ... 0x01: 2 0x00: 1 (use once) 15 tmode operational mode 1: impulse mode 0: sine mode 7 loop loopback tbsdata output to mdata inputs 1: enabled 0: disabled 14:12 rate[2:0] tbsdata and tbsclk output rate. 111: 2.048 mhz 110: 1.024 mhz 101: 512 khz 100: 256 khz 011: 128 khz 010: 64 khz 001: 32 khz 000: 4 khz 6 run run test bit stream 1: enabled 0: disabled 11 tsync synchronization 1: sync enabled 0: no sync 10:8 cdly[2:0] tbsclk output phase delay 111: 7/8 period 110: 3/4 period 101: 5/8 period 100: 1/2 period 011: 3/8 period 010: 1/4 period 001: 1/8 period 000: none 5:0 ddly[5:0] tbsdata output delay 0x3f: 63 bits 0x3e: 62 bits ... 0x01: 1 bit 0x00: 0 bits ( no delay)
cs5376a 99 23.2.12 tbsgain : 0x2b (msb) 23 22 21 20 19 18 17 16 tgain23 tgain22 tgain21 tgain20 tgain19 tgain18 tgain17 tgain16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 tgain15 tgain14 tgain13 tgain12 tgain11 tgain10 tgain9 tgain8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 tgain7 tgain6 tgain5 tgain4 tgain3 tgain2 tgain1 tgain0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x2b -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 58. test bit stream gain register tbsgain bit definitions: 23:16 tgain[23:16] test bit stream gain upper byte 15:8 tgain[15:8] test bit stream gain middle byte 15:8 tgain[7:0] test bit stream gain lower byte
cs5376a 100 23.2.13 system1, system2 : 0x2c, 0x2d (msb) 23 22 21 20 19 18 17 16 sys23 sys22 sys21 sys20 sys19 sys18 sys17 sys16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 15 14 13 12 11 10 9 8 sys15 sys14 sys13 sys12 sys11 sys10 sys9 sys8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 7654321(lsb) 0 sys7 sys6 sys5 sys4 sys3 sys2 sys1 sys0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 df address: 0x2c -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 59. user defined system register system1 bit definitions: 23:16 sys[23:16] system register upper byte 15:8 sys[15:8] system register middle byte 15:8 sys[7:0] system register lower byte
cs5376a 101 23.2.14 version : 0x2e (msb) 23 22 21 20 19 18 17 16 type7 type6 type5 type4 type3 type2 type1 type0 r/w r/w r/w r/w r/w r/w r/w r/w 01110110 15 14 13 12 11 10 9 8 hw7 hw6 hw5 hw4 hw3 hw2 hw1 hw0 r/w r/w r/w r/w r/w r/w r/w r/w 00000001 7654321(lsb) 0 rom7 rom6 rom5 rom4 rom3 rom2 rom1 rom0 r/w r/w r/w r/w r/w r/w r/w r/w 00000001 df address: 0x2e -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 60. hardware version id register version bit definitions: 23:16 type [7:0] chip type 76 - cs5376, cs5376a 15:8 hw [7:0] hardware revision 01 - cs5376 rev a 02 - cs5376 rev b 03 - cs5376a rev a 7:4 rom [7:0] rom version 01 - ver 1.0 02 - ver 2.0 03 - ver 3.0
cs5376a 102 23.2.15 selftest : 0x2f (msb) 23 22 21 20 19 18 17 16 -- -- -- -- eu3 eu2 eu1 eu0 r/w r/w r/w r/w r/w r/w r/w r/w 00001010 15 14 13 12 11 10 9 8 dram3 dram2 dram1 dram0 pram3 pram2 pram1 pram0 r/w r/w r/w r/w r/w r/w r/w r/w 10101010 7654321(lsb) 0 drom3 drom2 drom1 drom0 prom3 prom2 prom1 prom0 r/w r/w r/w r/w r/w r/w r/w r/w 10101010 df address: 0x2f -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 61. self test result register selftest bit definitions: 23:20 -- reserved 15:12 dram [3:0] data ram test ?a?: pass ?f?: fail 7:4 drom [3:0] data rom test ?a?: pass ?f?: fail 19:16 eu [3:0] execution unit test ?a?: pass ?f?: fail 11:8 pram [3:0] program ram test ?a?: pass ?f?: fail 3:0 prom [3:0] program rom test ?a?: pass ?f?: fail
cs5376a 103 24. pin descriptions timeb clk sync sddat sdrdy sdclk sdtko sdtki trst tms tck tdi tdo gnd vd tbsclk tbsdata dnc vdd2 mclk/2 mclk msync mdata4 mflag4 mdata3 mflag3 mdata2 mflag2 mdata1 mflag1 gnd gnd2 boot reset vdd1 gnd1 sint mosi miso ssi sck1 sso gpio11:eecs gpio10 gpio9 gpio8 gpio7 gpio6 vd gnd gnd2 gpio5 gpio4:cs4 gpio3:cs3 gpio2:cs2 gpio1:cs1 gpio0:cs0 sck2 so si1 si2 si3 si4 vdd2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425 26 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 cs5376a 64-pin tqfp
cs5376a 104 pin name pin number pin type pin description jtag port trst 1 input jtag reset, active low. connect to gnd if jtag is not used. tms 2 input jtag test mode select. tck 3 input jtag clock input. tdi 4 input jtag data input. tdo 5 output jtag data output. test bit stream tbsclk 8 output test bit stream clock output. tbsdata 9 output test bit stream data output. no connect dnc 10 n/a do not connect. modulator interface mclk/2 12 output modulator clock output, half rate. mclk 13 output modulator clock output, full rate. msync 14 output modulator sync output. mdata[4:1] 15, 17, 19, 21 input modulator data inputs. mflag[4:1] 16, 18, 20, 22 input modulator flag inputs. serial peripheral interface 2 si[4:1] 26, 27, 28, 29 input spi 2 data inputs. so 30 output spi 2 data output. sck2 31 output spi 2 clock output. general purpose input / output gpio[0:4]:cs[0:4] 32, 33, 34, 35, 36 input / output general purpose i/o with spi 2 chip selects. gpio[5:10] 37, 41, 42, 43, 44, 45 input / output general purpose i/o. gpio11:eecs 46 input / output general purpose i/o with boot eeprom chip select. serial peripheral interface 1 47 output spi 1 slave select output, active low. sck1 48 input / output spi 1 serial clock input / output. 49 input spi 1 slave select input, active low. miso 50 input / output spi 1 data, master in / slave out. open drain output requiring a 10 k ? pull-up. mosi 51 input / output spi 1 data, master out / slave in. 52 output spi 1 serial interrupt output, active low. reset control 55 input reset, active low. boot 56 input boot mode select. time break timeb 57 input time break input. sso ssi sint reset
cs5376a 105 clock and synchronization clk 58 input clock input, nominal 32.768 mhz. sync 59 input sync input. serial data port sddat 60 output sd port data output. sdrdy 61 output sd port data ready, active low. open drain output requiring a 10 k ? pull-up. sdclk 62 input sd port clock input. sdtko 63 output sd port token output. sdtki 64 input sd port token input. power supplies vdd1 54 supply pin power supply for pins 1 - 5 and 41 - 64. vdd2 11, 25 supply pin power supplies for pins 8 - 37. vd 7, 40 supply logic core power supplies. gnd1, gnd2, gnd 6, 23, 24, 38, 39, 53 supply digital grounds. pin name pin number pin type pin description
cs5376a 106 25. package dimensions inches millimeters dim min max min max a --- 0.063 --- 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.461 0.484 11.70 12.30 d1 0.390 0.398 9.90 10.10 e 0.461 0.484 11.70 12.30 e1 0.390 0.398 9.90 10.10 e* 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 64l tqfp package drawing e1 e d1 d 1 e l b a1 a
cs5376a 107 26. document revisions revision date changes pp1 september 2003 initial ?preliminary product? release. f1 february 2004 update group delay on page 50, power consumption on page 14 and miso read timing on page 15. add tbs impulse data on page 66 and mosi pull-up on page 32. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advis ed to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all product s are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, a nd limitation of liability. no re- sponsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufactu re or sale of any items, or for in- fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this informat ion, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. ci rrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organ ization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general dist ribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized or warrant- ed for use in aircraft systems, military applications, products surgically implanted into the body, life support prod- ucts or other critical applications (including medical devices, aircraft systems or components and personal or automotive safety or security devices). inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and oth- er agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trade- marks or service marks of their respective owners.

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